公开(公告)号：US09490009B2

公开(公告)日：2016-11-08

申请号：US14987309

申请日：2016-01-04

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Gary Bela Bronner ,  Frederick A. Ware

IPC: G11C16/04 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0097 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/75 ,  G11C2213/78 ,  G11C2213/79

Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.

Abstract translation: 存储单元包括第一电阻性存储器元件，在公共节点处与第一电阻式存储器元件电耦合的第二电阻存储元件，以及包括与公共节点电耦合的输入端的开关元件，该开关元件包括驱动器配置 在一个或多个操作期间浮动。

公开(公告)号：US09489323B2

公开(公告)日：2016-11-08

申请号：US14182986

申请日：2014-02-18

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

IPC: G06F13/00 ,  G06F12/00 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4022 ,  G06F12/00 ,  G06F13/00 ,  G06F13/1673 ,  G06F13/1694

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Abstract translation: 存储器模块包括数据接口，该数据接口包括多个数据线和耦合在数据接口和到一个或多个存储器的数据路径之间的多个可配置开关。 可以通过启用或禁用可配置开关的不同子集来配置内存模块的有效宽度。 可配置开关可以由手动开关，存储器模块上的缓冲器，外部存储器控制器或存储器模块上的存储器来控制。

公开(公告)号：US09466568B2

公开(公告)日：2016-10-11

申请号：US14683073

申请日：2015-04-09

Applicant: Rambus Inc.

Inventor： David Secker ,  Ling Yang ,  Chanh Tran ,  Ying Ji

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L25/18 ,  H01L23/522 ,  H03K5/1252 ,  H01L23/498

CPC classification number: H01L23/481 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/5286 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06541 ,  H01L2924/00014 ,  H03K5/1252 ,  H01L2224/0401

Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.

公开(公告)号：US09438826B2

公开(公告)日：2016-09-06

申请号：US14135014

申请日：2013-12-19

Applicant: Rambus Inc.

Inventor： Song Xue ,  Thomas Vogelsang

IPC: H01L27/146 ,  H04N5/335 ,  H04N5/347 ,  H04N5/357 ,  H04N5/3745 ,  H04N5/378

CPC classification number: H04N5/335 ,  H04N5/347 ,  H04N5/3575 ,  H04N5/37457 ,  H04N5/378

Abstract: An image sensor that includes a pixel array with image pixels with conditional reset circuitry. The pixels can be reset by a combination of row select and column reset signals, which implements the reset function while minimizing the number of extra signal lines. The pixels may also include pinned photodiodes. The manner in which the pinned photodiodes are used reduces noise and allows the quantization of the pixel circuits to be programmable.

Abstract translation: 一种图像传感器，其包括具有条件复位电路的图像像素的像素阵列。 可以通过行选择和列复位信号的组合来复位像素，其实现复位功能，同时最小化额外信号线的数量。 像素还可以包括固定的光电二极管。 使用钉扎光电二极管的方式降低了噪声，并允许像素电路的量化是可编程的。

公开(公告)号：US09437291B2

公开(公告)日：2016-09-06

申请号：US14605866

申请日：2015-01-26

Applicant: Rambus Inc.

Inventor： Bruce Lynn Bateman

IPC: G11C13/00 ,  G11C5/06

CPC classification number: G11C13/0038 ,  G11C5/06 ,  G11C13/003

Abstract: In one example, a current limited device is coupled between a source line of a memory cell array and a supply voltage, and configured to operate in a constant current mode during an access operation of a memory cell. An array control circuitry may be coupled to the memory cell array, and configured to control the constant current mode and supply an associated select bias voltage to the word line select transistor.

Abstract translation: 在一个示例中，电流限制器件耦合在存储器单元阵列的源极线和电源电压之间，并且被配置为在存储器单元的访问操作期间以恒定电流模式操作。 阵列控制电路可以耦合到存储单元阵列，并被配置为控制恒流模式并将相关的选择偏置电压提供给字线选择晶体管。

公开(公告)号：US09437279B2

公开(公告)日：2016-09-06

申请号：US14951190

申请日：2015-11-24

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/22 ,  G11C11/4076 ,  G06F13/16 ,  G06F13/42 ,  G11C8/18 ,  G11C7/10 ,  G06F1/10 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C11/409 ,  G11C2207/2254

Abstract: A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals.

Abstract translation: 时钟信号通过时钟信号线发送到第一和第二集成电路（IC）组件，该时钟信号在第一IC组件处具有第一到达时间，而在第二IC组件处具有第二较晚的到达时间。 在对应于时钟信号的转变的各个时刻，写入命令被发送到要被这些分量采样的第一和第二IC组件，并且与写命令相关联地将写数据发送到第一和第二IC组件。 第一和第二选通信号分别被发送到第一和第二IC组件，以便在这些组件中对第一和第二写入数据进行时间接收。 从多个相位偏移定时信号中选择第一和第二选通信号，以补偿时钟信号与第一和第二选通信号之间的各自的定时偏差。

公开(公告)号：US09437276B2

公开(公告)日：2016-09-06

申请号：US15132017

申请日：2016-04-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

IPC: G06F12/00 ,  G06F13/00 ,  G11C11/406 ,  G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1636 ,  G06F13/1689 ,  G06Q10/00 ,  G06Q20/00 ,  G11C7/02 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4061

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

公开(公告)号：US09419663B2

公开(公告)日：2016-08-16

申请号：US14552598

申请日：2014-11-25

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Brian S. Leibowitz ,  Jade M. Kizer ,  Thomas H. Greer ,  Akash Bansal

IPC: H03H7/30 ,  H04B1/12 ,  H04L25/03

CPC classification number: H04L25/03159 ,  H04B1/123 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03636

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

公开(公告)号：US20160231962A1

公开(公告)日：2016-08-11

申请号：US15022176

申请日：2014-09-23

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Thomas Vogelsang

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0638 ,  G06F3/0673 ,  G06F11/1076 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0411 ,  G11C2207/107

Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

Abstract translation: 存储器组件包括存储器组和用于接收读取 - 修改 - 写入命令的命令接口，其具有指示存储器组中的位置的相关联的读取地址，以及从读取的指示的存储器组中的位置访问读取数据 从接收到读 - 修改 - 写入命令的时间开始，或者与多个读 - 修改 - 写入命令重叠，可调节延迟时间之后的地址。 存储器组件还包括用于接收与读取 - 修改 - 写入命令相关联的写入数据的数据接口和用于将接收到的写入数据与读取的数据合并以形成合并数据的纠错电路，并将合并的数据写入到 由读取地址指示的存储体。

公开(公告)号：US09411767B2

公开(公告)日：2016-08-09

申请号：US14875433

申请日：2015-10-05

Applicant: Rambus Inc.

Inventor： Mark A. Horowitz ,  Craig E. Hampel ,  Alfredo Moncayo ,  Kevin S. Donnelly ,  Jared L. Zerbe

IPC: G06F13/42 ,  G06F13/40 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  H03K19/003 ,  H03K19/0185 ,  G11C19/00 ,  G06F13/10 ,  G06F3/06 ,  G06F13/16 ,  G06F13/364 ,  G06F12/10 ,  G11C16/32 ,  G06F12/02 ,  G11C7/22

CPC classification number: G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

Abstract: An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a value representative of a drive strength setting associated with the transmitter circuit such that the output driver outputs data in accordance with the drive strength setting. The integrated circuit device also includes a second register to store a value representative of an equalization setting associated with the transmitter circuit such that the output driver outputs data in accordance with the equalization setting. The integrated circuit device further includes a third register to store a value representative of a slew rate setting associated with the transmitter circuit such that the output driver outputs data in accordance with the slew rate setting.

Abstract translation: 集成电路装置包括具有输出驱动器的发送器电路。 集成电路装置包括第一寄存器，用于存储表示与发送器电路相关联的驱动强度设置的值，使得输出驱动器根据驱动强度设置输出数据。 集成电路装置还包括第二寄存器，用于存储代表与发送器电路相关联的均衡设置的值，使得输出驱动器根据均衡设置输出数据。 集成电路装置还包括第三寄存器，用于存储表示与发送器电路相关联的转换速率设置的值，使得输出驱动器根据转换速率设置输出数据。