中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

654 records (took 0.06 seconds)

    Semiconductor system, device and structure with heat removal
    373.
    发明授权
    Semiconductor system, device and structure with heat removal 有权
    半导体系统，器件和结构与散热

    公开(公告)号：US09099424B1

    公开(公告)日：2015-08-04

    申请号：US13869115

    申请日：2013-04-24

    Applicant: Monolithic 3D Inc.

    Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

    IPC: H01L29/72 ,  H01L23/373

    CPC classification number: H01L23/5225 ,  H01L23/3677 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A mobile system, including: a 3D device, the 3D device including: a first layer of first transistors, overlaid by at least one interconnection layer, where the interconnection layer comprises copper or aluminum; a second layer including second transistors, the second layer overlaying the interconnection layer, the second layer including: a plurality of electrical connections connecting the second transistors with the interconnection layer; and at least one thermally conductive and electrically non-conductive contact, the at least one thermally conductive and electrically non-conductive contact thermally connects the second layer to the top or bottom surface of the 3D device.

    Abstract translation: 一种移动系统，包括：3D设备，所述3D设备包括：由至少一个互连层覆盖的第一层第一晶体管，所述互连层包括铜或铝; 包括第二晶体管的第二层，覆盖所述互连层的所述第二层，所述第二层包括：将所述第二晶体管与所述互连层连接的多个电连接; 以及至少一个导热和非导电接触，所述至少一个导热和非导电接触将所述第二层热连接到所述3D器件的顶表面或底表面。

    Method of processing a semiconductor device
    375.
    发明授权
    Method of processing a semiconductor device 有权
    半导体器件的处理方法

    公开(公告)号：US09023688B1

    公开(公告)日：2015-05-05

    申请号：US14298917

    申请日：2014-06-07

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Albert Karl Henning

    IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/20 ,  H01L21/44 ,  H01L21/768

    CPC classification number: H01L27/0688 ,  H01L21/67109 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/481 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for processing a semiconductor device, the method including; providing a first semiconductor layer including first transistors; forming interconnection layers overlying the transistors, where the interconnection layers include copper or aluminum; forming a shielding heat conducting layer overlaying the interconnection layers; forming an isolation layer overlaying the shielding heat conducting layer; forming a second semiconductor layer overlying the isolation layer, and processing the second semiconductor layer at a temperature greater than about 400° C., where the interconnection layers are kept at a temperature below about 400° C.

    Abstract translation: 一种半导体器件的处理方法，该方法包括： 提供包括第一晶体管的第一半导体层; 形成覆盖晶体管的互连层，其中互连层包括铜或铝; 形成覆盖所述互连层的屏蔽导热层; 形成覆盖所述屏蔽导热层的隔离层; 形成覆盖隔离层的第二半导体层，以及在大于约400℃的温度下处理第二半导体层，其中互连层保持在低于约400℃的温度。

    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH LOGIC AND MEMORY
    379.
    发明申请
    3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH LOGIC AND MEMORY 有权

    公开(公告)号：US20250126794A1

    公开(公告)日：2025-04-17

    申请号：US18991631

    申请日：2024-12-22

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han

    IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B53/20 ,  H10D30/63 ,  H10D30/69 ,  H10D62/834 ,  H10D64/64 ,  H10D89/10

    Abstract: A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and a redundancy control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.

    3D MEMORY DEVICES AND STRUCTURES WITH MEMORY ARRAYS AND METAL LAYERS
    380.
    发明申请
    3D MEMORY DEVICES AND STRUCTURES WITH MEMORY ARRAYS AND METAL LAYERS 有权

    公开(公告)号：US20250098182A1

    公开(公告)日：2025-03-20

    申请号：US18963630

    申请日：2024-11-28

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A semiconductor device including: a first level including at least four independently controlled first memory arrays, where the first level includes first transistors; a second level disposed on top of the first level, where the second level includes second memory arrays; and a third level disposed on top of the second level, where the third level includes third transistors, at least one metal layer, and third memory arrays; a fourth level disposed on top of the third level, where the fourth level includes fourth transistors, another at least one metal layer, and is bonded to the third level, where the bonded includes metal-to-metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes; and a via connection through the second level and the third level, and where the fourth level includes at least one SRAM memory array.

Patent Agency Ranking