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    Silicon carrier including an integrated heater for die rework and wafer probe
    33.
    发明授权
    Silicon carrier including an integrated heater for die rework and wafer probe 有权
    硅载体包括用于模具返修的集成加热器和晶片探针

    公开(公告)号：US07474540B1

    公开(公告)日：2009-01-06

    申请号：US11972388

    申请日：2008-01-10

    Applicant: Bing Dang ,  Steven L. Wright

    Inventor： Bing Dang ,  Steven L. Wright

    IPC: H05K1/11

    CPC classification number: H01L23/345 ,  H01L23/147 ,  H01L23/5384 ,  H01L24/81 ,  H01L24/98 ,  H01L25/0655 ,  H01L2224/16235 ,  H01L2224/81234 ,  H01L2224/81815 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  Y10T29/4913 ,  H01L2924/00

    Abstract: A silicon carrier package includes a multi-layer member having at least a first layer and a second layer. A first electronic component includes a plurality of connector members that establish a first bond electrically interconnecting the first electronic component to the multi-layer member. A second electronic component includes a plurality of connector members that establish a second bond electrically interconnecting the second electronic component to the multi-layer member. At least one heating element is integrated into one of the first and second layers of the multi-layer member. The at least one heating element is selectively activated to loosen only one of the first and second bonds to facilitate removal of only one of the first and second electronic components from the multi-layer member. The other of the first and second bonds remains intact.

    Abstract translation: 硅载体封装包括具有至少第一层和第二层的多层构件。 第一电子部件包括多个连接器构件，其建立将第一电子部件电连接到多层部件的第一接合部。 第二电子部件包括多个连接器构件，其建立将第二电子部件电连接到多层部件的第二接合部。 至少一个加热元件集成到多层构件的第一层和第二层之一中。 选择性地激活至少一个加热元件以松开仅第一和第二键中的一个，以便于从多层构件中仅去除第一和第二电子部件中的仅一个。 第一和第二债券中的另一个保持不变。

    Transferable Probe Tips
    37.
    发明申请
    Transferable Probe Tips 有权
    可转移探头技巧

    公开(公告)号：US20120279287A1

    公开(公告)日：2012-11-08

    申请号：US13101253

    申请日：2011-05-05

    Applicant: Paul S. Andry ,  Bing Dang ,  Steven L. Wright

    Inventor： Paul S. Andry ,  Bing Dang ,  Steven L. Wright

    IPC: G01B5/28 ,  B05D5/00 ,  C23F1/00

    CPC classification number: G01B5/28 ,  B81B2201/12 ,  B81C3/001 ,  B81C2201/0194 ,  G01Q40/02 ,  G01Q70/14 ,  G01Q70/16 ,  G01R1/067 ,  G01R1/06738 ,  G01R1/07378 ,  G01R3/00 ,  G03F7/00

    Abstract: Transferable probe tips including a metallic probe, a delamination layer covering a portion of the metallic probe, and a bonding alloy, wherein the bonding alloy contacts the metallic probe at a portion of the probe that is not covered by the delamination layer are provided herein. Also, techniques for creating a transferable probe tip are provided, including etching a handler substrate to form one or more via arrays, depositing a delamination layer in each via array, depositing one or more metals in each via array to form a probe tip structure, and depositing a bonding alloy on a portion of the probe tip structure that is not covered by the delamination layer. Additionally, techniques for transferring transferable probe tips are provided, including removing a handler substrate from a probe tip structure, and transferring the probe tip structure via flip-chip joining the probe tip structure to a target probe head substrate.

    Abstract translation: 本发明提供了包括金属探针，覆盖金属探针的一部分的分层和可接合的探针尖端，以及接合合金，其中接合合金在探针的未被分层的覆盖部分处接触金属探针。 此外，提供了用于产生可转移探针尖端的技术，包括蚀刻处理器衬底以形成一个或多个通孔阵列，在每个通孔阵列中沉积分层，在每个通孔阵列中沉积一个或多个金属以形成探针尖端结构， 以及在未被分层层覆盖的探针尖端结构的一部分上沉积接合合金。 此外，提供了用于传送可转移的探针尖端的技术，包括从探针尖端结构去除处理器基底，以及通过将探针尖端结构连接到目标探针头基底的倒装芯片来传送探针尖端结构。

    Assembly Method For Reworkable Chip Stacking With Conductive Film
    39.
    发明申请
    Assembly Method For Reworkable Chip Stacking With Conductive Film 审中-公开
    带导电膜的可重复芯片堆叠的装配方法

    公开(公告)号：US20090181476A1

    公开(公告)日：2009-07-16

    申请号：US11972129

    申请日：2008-01-10

    Applicant: Stephen L. Buchwalter ,  Bing Dang ,  Claudius Feger ,  Peter A. Gruber ,  John Knickerbocker

    Inventor： Stephen L. Buchwalter ,  Bing Dang ,  Claudius Feger ,  Peter A. Gruber ,  John Knickerbocker

    IPC: H01L21/02

    CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of stacking a chip, including an integrated circuit, onto a substrate including applying an anisotropic conductive film (ACF) or a solder-filled conductive film onto a surface thereof, the surface being configured to electrically couple to the film, placing the chip onto the film, the chip being configured to electrically couple to the film, compressively pressurizing the chip, the film and the surface such that the chip is electrically coupled to the surface via the film,, testing the chip to determine whether the chip is operating normally, reworking the placement of the chip onto the film and repeating the compressive pressurization if the chip is determined to not be operating normally, repeating the testing to determine whether the chip is operating normally, and once the chip is determined to be operating normally, bonding the chip, the film and the surface.

    Abstract translation: 一种将包括集成电路的芯片堆叠在基板上的方法，包括将各向异性导电膜（ACF）或焊料填充导电膜施加到其表面上，该表面被配置为电耦合到膜，将芯片 芯片被配置为电耦合到膜，对芯片，膜和表面进行压缩加压，使得芯片经由膜电耦合到表面，测试芯片以确定芯片是否正在操作 通常，如果芯片被确定为不正常工作，重复测试以确定芯片是否正常工作，并且一旦芯片确定正常工作，则将芯片放置在膜上并重复压缩加压， 粘合芯片，薄膜和表面。

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