Semiconductor device and method of manufacturing the same
    31.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号:US08742479B2

    公开(公告)日:2014-06-03

    申请号:US13475325

    申请日:2012-05-18

    申请人: Kouichi Nagai

    发明人: Kouichi Nagai

    IPC分类号: H01L27/115

    摘要: A transistor is formed on a semiconductor substrate, and thereafter a first insulating film is formed. Subsequently, a ferroelectric capacitor is formed on the first insulating film, and then a second insulating film is formed on the ferroelectric capacitor. Thereafter, the upper surface of the second insulating film is planarized. Subsequently, a contact hole which reaches one of impurity regions of the transistor is formed, and thus a plug is formed by embedding a conductor in the contact hole. Thereafter, a hydrogen barrier layer is formed of aluminum oxide or the like. Then, a third insulating film is formed on the hydrogen barrier layer. Subsequently, contact holes which are connected to the ferroelectric capacitor and the plug are formed. Thereafter, a conductor is embedded in the contact holes, and thus interconnections are formed.

    摘要翻译: 在半导体衬底上形成晶体管,然后形成第一绝缘膜。 随后,在第一绝缘膜上形成铁电电容器,然后在铁电电容器上形成第二绝缘膜。 此后,第二绝缘膜的上表面被平坦化。 随后,形成到达晶体管的一个杂质区的接触孔,因此通过在导电孔中嵌入导体而形成插头。 此后,由铝氧化物等形成氢阻挡层。 然后,在氢阻挡层上形成第三绝缘膜。 随后,形成与铁电电容器和插头连接的接触孔。 此后,导体嵌入在接触孔中,因此形成互连。

    Film thickness monitoring structure for semiconductor substrate
    33.
    发明授权
    Film thickness monitoring structure for semiconductor substrate 有权
    半导体衬底膜厚监测结构

    公开(公告)号:US08581249B2

    公开(公告)日:2013-11-12

    申请号:US12461794

    申请日:2009-08-25

    摘要: A semiconductor substrate includes a wafer, a first stepped structure formed of plural stepped parts formed on a surface of the wafer with a first area occupation ratio, a second stepped structure formed of plural stepped parts formed on the surface of the wafer with a second, different area occupation ratio, and an interlayer insulation film formed on the surface so as to cover the first and second stepped structures, the interlayer insulation film having a planarized top surface, wherein there are provided at least first and second film-thickness monitoring patterns for monitoring film thickness on the surface in a manner covered by the interlayer insulation film, a first pattern group is formed on the surface such that the first pattern group comprises plural patterns disposed so as to surround the first film-thickness monitoring pattern, a second pattern group is formed on the surface such that the second pattern group comprises plural patterns disposed so as to surround the second film-thickness monitoring pattern, the first film-thickness monitoring pattern and the first pattern group having a third area occupation ratio on the surface, while the second film-thickness monitoring pattern and the second pattern group having a fourth area occupation ratio on the surface, wherein the third area occupation ratio is different from the fourth area occupation ratio.

    摘要翻译: 半导体衬底包括晶片,由形成在具有第一占区率的晶片的表面上的多个阶梯部分形成的第一阶梯结构,由形成在晶片的表面上的多个阶梯部分构成的第二阶梯结构, 不同的面积占有率,以及形成在表面上以覆盖第一和第二阶梯结构的层间绝缘膜,该层间绝缘膜具有平坦化的顶表面,其中至少设置有第一和第二膜厚监测图案, 以层间绝缘膜覆盖的方式监测表面上的膜厚度,在表面上形成第一图案组,使得第一图案组包括以围绕第一膜厚度监测图案设置的多个图案,第二图案 组形成在表面上,使得第二图案组包括以围绕第二图案设置的多个图案 膜厚监测图案,第一膜厚监测图案和表面具有第三区域占有率的第一图案组,而表面上具有第四区域占​​有率的第二膜厚监测图案和第二图案组 ,其中所述第三区域占有率与所述第四区域占​​有率不同。

    Semiconductor device including a circuit area and a monitor area having a plurality of monitor layers and method for manufacturing the same
    35.
    发明授权
    Semiconductor device including a circuit area and a monitor area having a plurality of monitor layers and method for manufacturing the same 有权
    包括具有多个监视层的电路区域和监视区域的半导体装置及其制造方法

    公开(公告)号:US08334533B2

    公开(公告)日:2012-12-18

    申请号:US11855482

    申请日:2007-09-14

    申请人: Kouichi Nagai

    发明人: Kouichi Nagai

    IPC分类号: H01L29/10

    摘要: In a circuit area wherein a semiconductor integrated circuit is to be formed, an isolation insulating film is formed on a surface of a semiconductor substrate (11), and, at the same time, five isolation insulating films (12m) extending in one specific direction are formed within a monitor area (1) at a fixed spacing. Then, a gate insulation film and a gate electrode are formed within the circuit area on the semiconductor substrate (11), and, at the same time, five gate insulation films (13m) and five gate electrodes (14m) extending in the same direction as the isolation insulating films (12m) are formed within the monitor area (1) at the same spacing as that of the isolation insulating films (12m).

    摘要翻译: 在要形成半导体集成电路的电路区域中,在半导体衬底(11)的表面上形成隔离绝缘膜,同时,在一个特定方向上延伸的隔离绝缘膜(12m) 以固定的间隔形成在监视器区域(1)内。 然后,在半导体基板(11)的电路区域内形成栅极绝缘膜和栅电极,同时,在同一方向上延伸有五个栅极绝缘膜(13m)和五个栅极电极(14m) 因为隔离绝缘膜(12m)以与隔离绝缘膜(12m)相同的间隔形成在监视区域(1)内。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    36.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号:US20120244642A1

    公开(公告)日:2012-09-27

    申请号:US13491737

    申请日:2012-06-08

    申请人: Kouichi Nagai

    发明人: Kouichi Nagai

    IPC分类号: H01L21/02

    摘要: A method for manufacturing a semiconductor device including a semiconductor substrate having transistors formed thereon, a first interlayer insulating film formed above the semiconductor substrate and the transistors, a ferroelectric capacitor formed above the first interlayer insulating film, a second interlayer insulating film formed above the first interlayer insulating film and the ferroelectric capacitor, a first metal wiring formed on the second interlayer insulating film, and a protection film formed on an upper surface of the wiring but not on a side surface of the wiring.

    摘要翻译: 一种制造半导体器件的方法,该半导体器件包括其上形成有晶体管的半导体衬底,形成在半导体衬底上的第一层间绝缘膜和晶体管,形成在第一层间绝缘膜上方的铁电电容器,形成在第一层间绝缘膜上的第二层间绝缘膜 层间绝缘膜和铁电电容器,形成在第二层间绝缘膜上的第一金属布线以及形成在布线的上表面而不是在布线的侧表面上的保护膜。

    FERROELECTRIC MEMORY AND MANUFACTURING METHOD THEREOF, AND MANUFACTURING METHOD OF FERROELECTRIC CAPACITOR
    37.
    发明申请
    FERROELECTRIC MEMORY AND MANUFACTURING METHOD THEREOF, AND MANUFACTURING METHOD OF FERROELECTRIC CAPACITOR 有权
    电磁记忆及其制造方法及其制造方法

    公开(公告)号:US20120171783A1

    公开(公告)日:2012-07-05

    申请号:US13412939

    申请日:2012-03-06

    申请人: Kouichi Nagai

    发明人: Kouichi Nagai

    IPC分类号: H01L21/02

    摘要: Provided is a ferroelectric memory including a silicon substrate, a transistor formed on the silicon substrate, and a ferroelectric capacitor formed above the transistor. The ferroelectric capacitor includes a lower electrode, a ferroelectric film formed on the lower electrode, an upper electrode formed on the ferroelectric film, and a metal film formed on the upper electrode.

    摘要翻译: 提供了一种铁电存储器,其包括硅衬底,形成在硅衬底上的晶体管和形成在晶体管上方的铁电电容器。 铁电电容器包括下电极,形成在下电极上的铁电膜,形成在强电介质膜上的上电极和形成在上电极上的金属膜。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    38.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号:US20120146185A1

    公开(公告)日:2012-06-14

    申请号:US13396129

    申请日:2012-02-14

    申请人: Kouichi Nagai

    发明人: Kouichi Nagai

    IPC分类号: H01L27/06 H01L21/02

    摘要: After the formation of a first interlayer insulating, an etching stopper film made of SiON is formed thereon. Subsequently, a contact hole extending from the upper surface of the etching stopper film and reaching a high concentration impurity region is formed, and a first plug is formed by filling W into the contact hole. Next, a ferroelectric capacitor, a second interlayer insulating film, and the like are formed. Thereafter, a contact hole extending from the upper surface of the interlayer insulating film and reaching the first plug is formed. Then, the contact hole is filled with W to form a second plug. With this, even when misalignment occurs, the interlayer insulating film is prevented from being etched.

    摘要翻译: 在形成第一层间绝缘之后,在其上形成由SiON制成的蚀刻阻挡膜。 随后,形成从蚀刻阻止膜的上表面延伸并达到高浓度杂质区的接触孔,并且通过将W填充到接触孔中而形成第一插塞。 接下来,形成铁电电容器,第二层间绝缘膜等。 此后,形成从层间绝缘膜的上表面延伸并到达第一插塞的接触孔。 然后,接触孔填充有W以形成第二插头。 由此,即使发生不对准,也可以防止层间绝缘膜被蚀刻。