公开(公告)号：US20100148320A1

公开(公告)日：2010-06-17

申请号：US12713514

申请日：2010-02-26

Applicant: Xueping Xu ,  Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes

Inventor： Xueping Xu ,  Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes

IPC: H01L29/04 ,  H01L21/306 ,  B26D3/00

CPC classification number: C30B29/403 ,  C30B25/18 ,  C30B29/406 ,  H01L29/045 ,  H01L29/2003 ,  Y10T83/0524 ,  Y10T428/31

Abstract: A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the direction predominantly toward a direction selected from the group consisting of and directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 μm2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm−2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. Both upper and lower surfaces may be offcut. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.

Abstract translation: III-V族氮化物，例如GaN，衬底，其包括从<0001>方向切除的（0001）表面主要朝向选自<10-10>和<11-20>方向的方向切割 在约0.2至约10度的范围内的角度，其中该表面具有通过50×50μm2 AFM扫描测量的RMS粗糙度小于1nm，位错密度小于3E6cm-2。 可以通过在对应的邻位异质外延基底（例如切断蓝宝石）上的基底主体的切削研磨或生长来对对应的原子块或晶片坯料进行切割切片来形成基底。 上表面和下表面都可以被切断。 在制造III-V族氮化物微电子和光电子器件时，该衬底有效地用于同质外延沉积。

公开(公告)号：US20070138505A1

公开(公告)日：2007-06-21

申请号：US11606624

申请日：2006-11-30

Applicant: Edward Preble ,  Lianghong Liu ,  Andrew Hanser ,  N. Williams ,  Xueping Xu

Inventor： Edward Preble ,  Lianghong Liu ,  Andrew Hanser ,  N. Williams ,  Xueping Xu

IPC: H01L31/00 ,  H01L21/00

CPC classification number: H01L21/02694 ,  C30B25/02 ,  C30B25/18 ,  C30B25/183 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/02581 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02631 ,  H01L29/04 ,  H01L29/0688 ,  H01L29/2003 ,  H01L33/007 ,  H01L33/30 ,  H01L33/32

Abstract: In a method for making a low-defect single-crystal GaN film, an epitaxial nitride layer is deposited on a substrate. A first GaN layer is grown on the epitaxial nitride layer by HVPE under a growth condition that promotes the formation of pits, wherein after growing the first GaN layer the GaN film surface morphology is rough and pitted. A second GaN layer is grown on the first GaN layer to form a GaN film on the substrate. The second GaN layer is grown by HVPE under a growth condition that promotes filling of the pits, and after growing the second GaN layer the GaN film surface morphology is essentially pit-free. A GaN film having a characteristic dimension of about 2 inches or greater, and a thickness normal ranging from approximately 10 to approximately 250 microns, includes a pit-free surface, the threading dislocation density being less than 1×108 cm−2.

Abstract translation: 在制造低缺陷单晶GaN膜的方法中，在衬底上沉积外延氮化物层。 在促进凹坑形成的生长条件下，通过HVPE在外延氮化物层上生长第一GaN层，其中在生长第一GaN层之后，GaN膜表面形貌粗糙和凹陷。 在第一GaN层上生长第二GaN层，以在衬底上形成GaN膜。 第二GaN层通过HVPE在促进凹坑填充的生长条件下生长，并且在生长第二GaN层之后，GaN膜表面形态基本上是无凹坑的。 具有约2英寸或更大的特征尺寸和约10至约250微米的厚度法线的GaN膜包括无凹坑表面，穿透位错密度小于1×10 8 cm -2。

公开(公告)号：US20060228584A1

公开(公告)日：2006-10-12

申请号：US11431990

申请日：2006-05-11

Applicant: Xueping Xu ,  Robert Vaudo ,  Jeffrey Flynn ,  George Brandes

Inventor： Xueping Xu ,  Robert Vaudo ,  Jeffrey Flynn ,  George Brandes

IPC: B32B9/00 ,  B32B19/00

CPC classification number: C30B29/403 ,  C30B25/18 ,  C30B29/406 ,  H01L29/045 ,  H01L29/2003 ,  Y10T83/0524 ,  Y10T428/31

Abstract: A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the direction predominantly toward a direction selected from the group consisting of and directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 μm2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm−2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.

Abstract translation: III-V族氮化物，例如GaN，衬底，其包括从<0001>方向切除的（0001）表面主要朝向选自<10-10>和<11-20>方向的方向切割 在约0.2至约10度的范围内的角度，其中表面具有通过50×50μm2μmAFM扫描测量的RMS粗糙度小于1nm，位错密度小于 3E6厘米-2。 可以通过在对应的邻位异质外延基底（例如切断蓝宝石）上的基底主体的切削研磨或生长来对对应的原子块或晶片坯料进行切割切片来形成基底。 在制造III-V族氮化物微电子和光电子器件时，该衬底有效地用于同质外延沉积。

公开(公告)号：US07118813B2

公开(公告)日：2006-10-10

申请号：US10714307

申请日：2003-11-14

Applicant: Xueping Xu ,  Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes

Inventor： Xueping Xu ,  Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes

IPC: C30B23/02 ,  C30B29/38 ,  C30B29/40 ,  B32B9/00

CPC classification number: C30B29/403 ,  C30B25/18 ,  C30B29/406 ,  H01L29/045 ,  H01L29/2003 ,  Y10T83/0524 ,  Y10T428/31

Abstract: A III–V nitride, e.g., GaN, substrate including a (0001) surface offcut from the direction predominantly toward a direction selected from the group consisting of and directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 μm2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm−2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III–V nitride-based microelectronic and opto-electronic devices.

公开(公告)号：US07097707B2

公开(公告)日：2006-08-29

申请号：US10328223

申请日：2002-12-23

Applicant: Xueping Xu

Inventor： Xueping Xu

IPC: C30B15/04

CPC classification number: C30B29/40 ,  C30B11/00 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146

Abstract: A method of making a single crystal GaN boule, comprising contacting a GaN seed wafer with a GaN source environment under process conditions including a thermal gradient in the GaN source environment producing growth of gallium nitride on the GaN seed wafer, thereby forming the GaN boule. The GaN source environment in various implementations includes gallium melt in an ambient atmosphere of nitrogen or ammonia, or alternatively, supercritical ammonia containing solubilized GaN. The method produces single crystal GaN boules >10 millimeters in diameter, of device quality suitable for production of GaN wafers useful in the fabrication of microelectronic, optoelectronic and microelectromechanical devices and device precursor structures therefor.

Abstract translation: 一种制造单晶GaN棒的方法，包括使GaN籽晶片与GaN源环境在包括GaN源环境中的热梯度的工艺条件下接触，从而在GaN晶种晶片上产生氮化镓的生长，由此形成GaN晶粒。 各种实施方案中的GaN源环境包括在氮或氨的环境气氛中的镓熔体，或者替代地，含有溶解的GaN的超临界氨。 该方法产生直径> 10毫微米的单晶GaN衬底，适用于生产用于制造微电子，光电子和微机电器件及其器件前体结构的GaN晶圆的器件质量。

公开(公告)号：US06951695B2

公开(公告)日：2005-10-04

申请号：US10272761

申请日：2002-10-17

Applicant: Xueping Xu ,  Robert P. Vaudo

Inventor： Xueping Xu ,  Robert P. Vaudo

IPC: C30B25/18 ,  C09G1/02 ,  C30B29/38 ,  C30B29/40 ,  C30B33/00 ,  G01Q30/12 ,  G01Q60/00 ,  H01L21/304 ,  H01L21/306 ,  H01L33/00 ,  B32B9/04 ,  B24B1/00 ,  H01L21/302

CPC classification number: C30B33/00 ,  C09G1/02 ,  C09K3/1409 ,  C09K3/1463 ,  C30B25/02 ,  C30B29/403 ,  H01L21/02005 ,  H01L21/02019 ,  H01L21/02024 ,  H01L21/30617 ,  H01L33/0075 ,  Y10T428/21

Abstract: AlxGayInzN, wherein 0≦x≦1, 0≦y≦1, 0≦z≦1, and x+y+z=1, characterized by a root mean square surface roughness of less than 1 nm in a 10×10 μm2 area. The AlxGayInzN may be in the form of a wafer, which is chemically mechanically polished (CMP) using a CMP slurry comprising abrasive particles, such as silica or alumina, and an acid or a base. High quality AlxGayInzN wafers can be fabricated by steps including lapping, mechanical polishing, and reducing internal stress of said wafer by thermal annealing or chemical etching for further enhancement of its surface quality. CMP processing may be usefully employed to highlight crystal defects of an AlxGayInzN wafer.

Abstract translation: 其中0 <= x <=1,0,0≤y≤1,0

公开(公告)号：US06488767B1

公开(公告)日：2002-12-03

申请号：US09877437

申请日：2001-06-08

Applicant: Xueping Xu ,  Robert P. Vaudo

Inventor： Xueping Xu ,  Robert P. Vaudo

IPC: C30B2502

CPC classification number: C30B33/00 ,  C09G1/02 ,  C09K3/1409 ,  C09K3/1463 ,  C30B25/02 ,  C30B29/403 ,  H01L21/02005 ,  H01L21/02019 ,  H01L21/02024 ,  H01L21/30617 ,  H01L33/0075 ,  Y10T428/21

Abstract: A high quality wafer comprising AlxGayInzN, wherein 0

Abstract translation: 包括AlxGayInzN的高品质晶片，其中0

公开(公告)号：US06268229B1

公开(公告)日：2001-07-31

申请号：US09461693

申请日：1999-12-14

Applicant: George R. Brandes ,  Charles P. Beetz ,  Xueping Xu ,  Swayambu V. Ramani ,  Ronald S. Besser

Inventor： George R. Brandes ,  Charles P. Beetz ,  Xueping Xu ,  Swayambu V. Ramani ,  Ronald S. Besser

IPC: H01L2100

CPC classification number: H01L28/20 ,  H01J1/3042 ,  H01J2201/30403 ,  H01J2201/319 ,  H01J2329/00 ,  H01L31/03765 ,  Y02E10/548 ,  Y10S438/931

Abstract: Integrated circuits, including field emission devices, have a resistor element of amorphous SixC1-x wherein 0

Abstract translation: 包括场致发射器件的集成电路具有0≤x≤1的无定形六C1-x的电阻元件，并且其中所述SixC1-x包含选自氢，卤素，氮，氧，硫中的至少一种杂质 ，硒，过渡金属，硼，铝，磷，镓，砷，锂，铍，钠和镁。

公开(公告)号：US6031250A

公开(公告)日：2000-02-29

申请号：US575484

申请日：1995-12-20

Applicant: George R. Brandes ,  Charles P. Beetz ,  Xueping Xu ,  Swayambu V. Ramani ,  Ronald S. Besser

Inventor： George R. Brandes ,  Charles P. Beetz ,  Xueping Xu ,  Swayambu V. Ramani ,  Ronald S. Besser

IPC: H01J9/02 ,  H01J1/304 ,  H01J19/24 ,  H01J21/10 ,  H01J29/04 ,  H01J31/12 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L31/0376 ,  H01L31/0312

CPC classification number: H01L28/20 ,  H01J1/3042 ,  H01L31/03765 ,  H01J2201/30403 ,  H01J2201/319 ,  H01J2329/00 ,  Y02E10/548 ,  Y10S438/931

Abstract: Integrated circuits, including field emission devices, have a resistor element of amorphous Si.sub.x C.sub.1-x wherein 0

Abstract translation: 包括场致发射器件的集成电路具有0≤x≤1的无定形六C1-x的电阻元件，并且其中所述SixC1-x包含选自氢，卤素，氮，氧，硫中的至少一种杂质 ，硒，过渡金属，硼，铝，磷，镓，砷，锂，铍，钠和镁。

公开(公告)号：US08435879B2

公开(公告)日：2013-05-07

申请号：US12085857

申请日：2006-11-30

Applicant: Andrew D. Hanser ,  Lianghong Liu ,  Edward A. Preble ,  Denis Tsvetkov ,  Nathaniel Mark Williams ,  Xueping Xu

Inventor： Andrew D. Hanser ,  Lianghong Liu ,  Edward A. Preble ,  Denis Tsvetkov ,  Nathaniel Mark Williams ,  Xueping Xu

IPC: H01L21/28

CPC classification number: H01L21/02694 ,  C30B25/02 ,  C30B25/18 ,  C30B25/183 ,  C30B29/403 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/02581 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02631 ,  H01L29/04 ,  H01L29/0688 ,  H01L29/2003 ,  H01L33/007 ,  H01L33/30 ,  H01L33/32

Abstract: Group III (Al, Ga, In)N single crystals, articles and films useful for producing optoelectronic devices (such as light emitting diodes (LEDs), laser diodes (LDs) and photodetectors) and electronic devices (such as high electron mobility transistors (HEMTs)) composed of III-V nitride compounds, and methods for fabricating such crystals, articles and films.

Abstract translation: 用于制造光电子器件（如发光二极管（LED），激光二极管（LD））和光电检测器的III族（Al，Ga，In）N单晶，制品和膜以及电子器件（如高电子迁移率晶体管 由III-V族氮化物组成的HEMT）以及制造这种晶体，制品和薄膜的方法。