公开(公告)号：US20170321320A1

公开(公告)日：2017-11-09

申请号：US15598687

申请日：2017-05-18

Applicant: Applied Materials, Inc.

Inventor： Sang-Ho YU ,  Kevin MORAES ,  Seshadri GANGULI ,  Hua CHUNG ,  See-Eng PHAN

IPC: C23C16/16 ,  H01L21/768 ,  H01L21/285 ,  C23C16/02 ,  H01L21/02 ,  C23C16/18 ,  H01L21/324

CPC classification number: C23C16/16 ,  C23C16/0218 ,  C23C16/18 ,  H01L21/02068 ,  H01L21/02074 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/324 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76862 ,  H01L21/76883

Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface. In another embodiment, a deposition-treatment cycle includes performing the vapor deposition process and subsequently a post-treatment process, which deposition-treatment cycle may be repeated to form multiple cobalt capping layers.

公开(公告)号：US20170178962A1

公开(公告)日：2017-06-22

申请号：US15391623

申请日：2016-12-27

Applicant: Applied Materials, Inc.

Inventor： Abhishek DUBE ,  Hua CHUNG ,  Jenn-Yue WANG ,  Xuebin LI ,  Yi-Chiau HUANG ,  Schubert S. CHU

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L29/7848 ,  H01L29/7851

Abstract: Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr.

公开(公告)号：US20160300715A1

公开(公告)日：2016-10-13

申请号：US15091332

申请日：2016-04-05

Applicant: Applied Materials, Inc.

Inventor： Abhishek DUBE ,  Xuebin LI ,  Yi-Chiau HUANG ,  Hua CHUNG ,  Schubert S. CHU

IPC: H01L21/02 ,  H01L29/10

CPC classification number: H01L21/02576 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636

Abstract: Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.

Abstract translation: 本公开的实施例一般涉及在增加的压力和降低的温度下在半导体器件上形成掺杂硅外延层的方法。 在一个实施例中，该方法包括将设置在处理室内的衬底加热至约550摄氏度至约800摄氏度的温度，将包含三氯硅烷（TCS），磷源和气体的硅源引入处理室 包括卤素，以及在所述衬底上沉积包含磷的含硅外延层，所述含硅外延层的磷浓度为约1×1021原子/立方厘米或更大，其中所述含硅外延层以室压力 约150托或更大。

公开(公告)号：US20160099178A1

公开(公告)日：2016-04-07

申请号：US14875013

申请日：2015-10-05

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Hua CHUNG

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/8258 ,  H01L21/306

CPC classification number: H01L21/02507 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/8258

Abstract: Methods and apparatus for forming FinFET structures are provided. Selective etching and deposition processes described herein may provide for FinFET manufacturing without the utilization of multiple patterning processes. Embodiments described herein also provide for fin material manufacturing methods for transitioning from silicon to III-V materials while maintaining acceptable crystal lattice orientations of the various materials utilized. Further embodiments provide etching apparatus which may be utilized to perform the methods described herein.

Abstract translation: 提供了用于形成FinFET结构的方法和装置。 本文所述的选择性蚀刻和沉积工艺可以提供FinFET制造而不利用多个图案化工艺。 本文描述的实施例还提供了用于从硅转变为III-V材料的翅片材料制造方法，同时保持所使用的各种材料的可接受的晶格取向。 另外的实施例提供可用于执行本文所述方法的蚀刻装置。

公开(公告)号：US20150372119A1

公开(公告)日：2015-12-24

申请号：US14320590

申请日：2014-06-30

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Hua CHUNG

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/324 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L29/66795 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32541 ,  H01J37/32568 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02359 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/265 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66666 ,  H01L29/775

Abstract: Embodiments of the present disclosure provide methods for forming nanowire structures with desired materials for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes performing an ion implantation process to dope dopants into a suspended nanowire structure on a substrate, the suspended nanowire includes multiple material layers having a spaced apart relationship repeatedly formed in the suspended nanowire structure, wherein the material layer predominantly comprises a first type of atoms formed therein, the dopants including a second type of atoms into the suspended nanowire structure, oxidating surfaces of the multiple material layers, and converting the first type of atoms in the material layer to the second type of atoms from the dopants doped therein.

Abstract translation: 本公开的实施例提供了用于形成用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠的所需材料的纳米线结构的方法。 在一个实例中，在衬底上形成纳米线结构的方法包括进行离子注入工艺以将掺杂剂掺杂到衬底上的悬浮的纳米线结构中，所述悬浮的纳米线包括在悬浮的纳米线结构中重复形成间隔关系的多个材料层 ，其中所述材料层主要包含在其中形成的第一类型的原子，所述掺杂剂包括到所述悬浮的纳米线结构中的第二类型的原子，所述多个材料层的氧化表面，以及将所述材料层中的所述第一类型的原子转化为 来自掺杂掺杂物的第二类型的原子。

公开(公告)号：US20150372118A1

公开(公告)日：2015-12-24

申请号：US14320559

申请日：2014-06-30

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Hua CHUNG

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/161 ,  H01L21/3065 ,  H01L29/06

CPC classification number: H01L29/66795 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32541 ,  H01J37/32568 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02359 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/265 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66666 ,  H01L29/775

Abstract: Embodiments of the present disclosure provide methods for forming nanowire structures with desired materials for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming nanowire structures on a substrate includes forming a multi-material layer on a substrate, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, the substrate further comprising a patterned hardmask layer disposed on the multi-material layer, etching the multi-material layer through openings defined by the patterned hardmask layer to expose sidewalls of the first and the second layer of the multi-material layer, and laterally and selectively etching the second layer from the substrate.

Abstract translation: 本公开的实施例提供了用于形成用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠的所需材料的纳米线结构的方法。 在一个实施方案中，在衬底上形成纳米线结构的方法包括在衬底上形成多材料层，其中所述多材料层包括第一层和第二层的重复对，所述衬底还包括图案化硬掩模层 设置在多材料层上，通过由图案化的硬掩模层限定的开口蚀刻多材料层，以暴露多材料层的第一和第二层的侧壁，并横向和选择性地从衬底上蚀刻第二层 。

公开(公告)号：US20150371852A1

公开(公告)日：2015-12-24

申请号：US14730194

申请日：2015-06-03

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Uday MITRA ,  Praburam GOPALRAJA ,  Srinivas D. NEMANI ,  Hua CHUNG

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528

CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816

Abstract: The present disclosure provides forming nanostructures with precision dimension control and minimum lithographic related errors for features with dimension under 14 nanometers and beyond. A self-aligned multiple spacer patterning (SAMSP) process is provided herein and the process utilizes minimum lithographic exposure process, but rather multiple deposition/etching process to incrementally reduce feature sizes formed in the mask along the manufacturing process, until a desired extreme small dimension nanostructures are formed in a mask layer.

Abstract translation: 本公开提供形成具有尺寸在14纳米以下的特征的精确尺寸控制和最小光刻相关误差的纳米结构。 本文提供了自对准多间隔图案（SAMSP）工艺，并且该工艺利用最小光刻曝光工艺，而是采用多次沉积/蚀刻工艺来逐渐减小沿制造工艺在掩模中形成的特征尺寸，直到期望的极小尺寸 在掩模层中形成纳米结构。

公开(公告)号：US20150325446A1

公开(公告)日：2015-11-12

申请号：US14682218

申请日：2015-04-09

Applicant: Applied Materials, Inc.

Inventor： Sang-Ho YU ,  Kevin MORAES ,  Seshadri GANGULI ,  Hua CHUNG ,  See-Eng PHAN

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/324

CPC classification number: C23C16/16 ,  C23C16/0218 ,  C23C16/18 ,  H01L21/02068 ,  H01L21/02074 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/324 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76862 ,  H01L21/76883

Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface. In another embodiment, a deposition-treatment cycle includes performing the vapor deposition process and subsequently a post-treatment process, which deposition-treatment cycle may be repeated to form multiple cobalt capping layers.

公开(公告)号：US20150140787A1

公开(公告)日：2015-05-21

申请号：US14548044

申请日：2014-11-19

Applicant: Applied Materials, Inc.

Inventor： Ying ZHANG ,  Hua CHUNG

IPC: H01L21/02 ,  H01L21/306

CPC classification number: H01L21/30604 ,  H01L21/02126 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31138 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/66818

Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps are performed on a substrate to provide a trench defining a mandrel structure. Sidewalls of the mandrel structure and a bottom surface of the trench are oxidized and subsequently etched to reduce a width of the mandrel structure. The oxidation and etching of the mandrel structure may be repeated until a desired width of the mandrel structure is achieved. A semiconducting material is subsequently deposited on a regrowth region of the mandrel structure to form a fin structure. The oxidizing and etching the mandrel structure provides a method for forming the fin structure which can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.

Abstract translation: 本文描述的实施例通常涉及形成次10nm节点FinFET的方法。 在基板上执行各种处理步骤，以提供限定心轴结构的沟槽。 心轴结构的侧壁和沟槽的底表面被氧化并随后被蚀刻以减小心轴结构的宽度。 可以重复心轴结构的氧化和蚀刻，直到实现心轴结构的期望宽度。 随后将半导体材料沉积在心轴结构的再生长区域上以形成翅片结构。 氧化和蚀刻心轴结构提供了一种用于形成翅片结构的方法，其可实现10nm以下的节点尺寸并提供越来越小的FinFET。

公开(公告)号：US20230036426A1

公开(公告)日：2023-02-02

申请号：US17961463

申请日：2022-10-06

Applicant: Applied Materials, Inc.

Inventor： Abhishek DUBE ,  Xuebin LI ,  Hua CHUNG ,  Flora Fong-Song CHANG

IPC: C30B25/18 ,  C30B29/06 ,  C30B33/12 ,  C23C16/02 ,  C23C16/56 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/67 ,  H01J37/32 ,  C23C16/24 ,  C23C16/54 ,  H01L21/687

Abstract: Embodiments of the present disclosure generally relate to methods for forming epitaxial layers on a semiconductor device. In one or more embodiments, methods include removing oxides from a substrate surface during a cleaning process, flowing a processing reagent containing a silicon source and exposing the substrate to the processing reagent during an epitaxy process, and stopping the flow of the processing reagent. The method also includes flowing a purging gas and pumping residues from the processing system, stopping the flow of the purge gas, flowing an etching gas and exposing the substrate to the etching gas. The etching gas contains hydrogen chloride and at least one germanium and/or chlorine compound. The method further includes stopping the flow of the at least one compound while continuing the flow of the hydrogen chloride and exposing the substrate to the hydrogen chloride and stopping the flow of the hydrogen chloride.