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公开(公告)号:US08623756B2
公开(公告)日:2014-01-07
申请号:US13167257
申请日:2011-06-23
申请人: Chita Chuang , Sheng-Yu Wu , Tin-Hao Kuo , Pei-Chun Tsai , Ming-Da Cheng , Chen-Shien Chen
发明人: Chita Chuang , Sheng-Yu Wu , Tin-Hao Kuo , Pei-Chun Tsai , Ming-Da Cheng , Chen-Shien Chen
IPC分类号: H01L21/283
CPC分类号: H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/11002 , H01L2224/1146 , H01L2224/11849 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13171 , H01L2224/13172 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/742 , H01L2224/81193 , H01L2224/81815 , H01L2224/94 , H01L2224/11 , H01L2924/00014 , H01L2924/00012 , H01L2224/81
摘要: A system and method for forming conductive connections is disclosed. An embodiment comprises forming conductive material on to contacts of a semiconductor substrate. The semiconductor substrate is then inverter such that the conductive material is beneath the semiconductor substrate, and the conductive material is reflowed to form a conductive bump. The reflow is performed using gravity in order to form a more uniform shape for the conductive bump.
摘要翻译: 公开了一种用于形成导电连接的系统和方法。 一个实施例包括在半导体衬底的触点上形成导电材料。 然后半导体衬底是反射器,使得导电材料在半导体衬底下方,并且导电材料被回流以形成导电凸块。 使用重力进行回流,以便为导电凸块形成更均匀的形状。
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公开(公告)号:US20120329264A1
公开(公告)日:2012-12-27
申请号:US13167257
申请日:2011-06-23
申请人: Chita Chuang , Sheng-Yu Wu , Tin-Hao Kuo , Pei-Chun Tsai , Ming-Da Cheng , Chen-Shien Chen
发明人: Chita Chuang , Sheng-Yu Wu , Tin-Hao Kuo , Pei-Chun Tsai , Ming-Da Cheng , Chen-Shien Chen
IPC分类号: H01L21/283
CPC分类号: H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/11002 , H01L2224/1146 , H01L2224/11849 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13171 , H01L2224/13172 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/742 , H01L2224/81193 , H01L2224/81815 , H01L2224/94 , H01L2224/11 , H01L2924/00014 , H01L2924/00012 , H01L2224/81
摘要: A system and method for forming conductive connections is disclosed. An embodiment comprises forming conductive material on to contacts of a semiconductor substrate. The semiconductor substrate is then inverter such that the conductive material is beneath the semiconductor substrate, and the conductive material is reflowed to form a conductive bump. The reflow is performed using gravity in order to form a more uniform shape for the conductive bump.
摘要翻译: 公开了一种用于形成导电连接的系统和方法。 一个实施例包括在半导体衬底的触点上形成导电材料。 然后半导体衬底是反射器,使得导电材料在半导体衬底下方,并且导电材料被回流以形成导电凸块。 使用重力进行回流,以便为导电凸块形成更均匀的形状。
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公开(公告)号:US20120199966A1
公开(公告)日:2012-08-09
申请号:US13023011
申请日:2011-02-08
申请人: Tin-Hao Kuo , Yu-Feng Chen , Chen-Shien Chen , Chen-Hua Yu , Sheng-Yu Wu , Chita Chuang
发明人: Tin-Hao Kuo , Yu-Feng Chen , Chen-Shien Chen , Chen-Hua Yu , Sheng-Yu Wu , Chita Chuang
CPC分类号: H01L24/13 , H01L23/3192 , H01L24/05 , H01L24/14 , H01L2224/0401 , H01L2224/05555 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05687 , H01L2224/1145 , H01L2224/11452 , H01L2224/13012 , H01L2224/13014 , H01L2224/13022 , H01L2224/13027 , H01L2224/13083 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/14141 , H01L2224/81192 , H01L2924/00013 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/00014 , H01L2924/04941 , H01L2924/04953 , H01L2924/0105 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00012 , H01L2924/00
摘要: An elongated bump structure for semiconductor devices is provided. An uppermost protective layer has an opening formed therethrough. A pillar is formed within the opening and extending over at least a portion of the uppermost protective layer. The portion extending over the uppermost protective layer exhibits a generally elongated shape. In an embodiment, the position of the opening relative to the portion of the bump structure extending over the uppermost protective layer is such that a ratio of a distance from an edge of the opening to an edge of the bump is greater than or equal to about 0.2. In another embodiment, the position of the opening is offset relative to center of the bump.
摘要翻译: 提供了用于半导体器件的细长凸块结构。 最上面的保护层具有通过其形成的开口。 在该开口内形成一个支柱,并延伸至最上层保护层的至少一部分。 在最上保护层上延伸的部分呈现大致细长的形状。 在一个实施例中,开口相对于在最上保护层上延伸的凸起结构的部分的位置使得从开口的边缘到凸起的边缘的距离的比例大于或等于约 0.2。 在另一个实施例中,开口的位置相对于凸块的中心偏移。
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公开(公告)号:US09093332B2
公开(公告)日:2015-07-28
申请号:US13023011
申请日:2011-02-08
申请人: Tin-Hao Kuo , Yu-Feng Chen , Chen-Shien Chen , Chen-Hua Yu , Sheng-Yu Wu , Chita Chuang
发明人: Tin-Hao Kuo , Yu-Feng Chen , Chen-Shien Chen , Chen-Hua Yu , Sheng-Yu Wu , Chita Chuang
CPC分类号: H01L24/13 , H01L23/3192 , H01L24/05 , H01L24/14 , H01L2224/0401 , H01L2224/05555 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05687 , H01L2224/1145 , H01L2224/11452 , H01L2224/13012 , H01L2224/13014 , H01L2224/13022 , H01L2224/13027 , H01L2224/13083 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/14141 , H01L2224/81192 , H01L2924/00013 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/00014 , H01L2924/04941 , H01L2924/04953 , H01L2924/0105 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00012 , H01L2924/00
摘要: An elongated bump structure for semiconductor devices is provided. An uppermost protective layer has an opening formed therethrough. A pillar is formed within the opening and extending over at least a portion of the uppermost protective layer. The portion extending over the uppermost protective layer exhibits a generally elongated shape. In an embodiment, the position of the opening relative to the portion of the bump structure extending over the uppermost protective layer is such that a ratio of a distance from an edge of the opening to an edge of the bump is greater than or equal to about 0.2. In another embodiment, the position of the opening is offset relative to center of the bump.
摘要翻译: 提供了用于半导体器件的细长凸块结构。 最上面的保护层具有通过其形成的开口。 在该开口内形成一个支柱,并延伸至最上层保护层的至少一部分。 在最上保护层上延伸的部分呈现大致细长的形状。 在一个实施例中,开口相对于在最上保护层上延伸的凸起结构的部分的位置使得从开口的边缘到凸起的边缘的距离的比例大于或等于约 0.2。 在另一个实施例中,开口的位置相对于凸块的中心偏移。
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公开(公告)号:US09425136B2
公开(公告)日:2016-08-23
申请号:US13449078
申请日:2012-04-17
申请人: Tin-Hao Kuo , Chen-Shien Chen , Mirng-Ji Lii , Chen-Hua Yu , Sheng-Yu Wu , Yao-Chun Chuang
发明人: Tin-Hao Kuo , Chen-Shien Chen , Mirng-Ji Lii , Chen-Hua Yu , Sheng-Yu Wu , Yao-Chun Chuang
IPC分类号: H01L29/49 , H01L23/498 , H01L23/00
CPC分类号: H01L24/13 , H01L23/49816 , H01L24/11 , H01L24/16 , H01L2224/0361 , H01L2224/03912 , H01L2224/11462 , H01L2224/11464 , H01L2224/11472 , H01L2224/11474 , H01L2224/11903 , H01L2224/13012 , H01L2224/13014 , H01L2224/13017 , H01L2224/13025 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13184 , H01L2224/16238 , H01L2224/81191 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/3512 , H01L2924/35121 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要: A pillar structure for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.
摘要翻译: 提供了一种用于衬底的柱结构。 支柱结构可以具有一个或多个层,其中每个层可以具有圆锥形或球形。 在一个实施例中,柱结构用于跟踪跟踪(BOT)配置。 支柱结构在平面图中可以具有圆形或细长形状。 衬底可以耦合到另一衬底。 在一个实施例中,另一衬底可以具有凸起的导电迹线,柱结构可以联接到该导电迹线上。
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公开(公告)号:US07871860B1
公开(公告)日:2011-01-18
申请号:US12620321
申请日:2009-11-17
申请人: Han-Ping Pu , Tsung-Shu Lin , Chen-Shien Chen
发明人: Han-Ping Pu , Tsung-Shu Lin , Chen-Shien Chen
CPC分类号: H01L24/81 , H01L21/563 , H01L24/16 , H01L2224/73203 , H01L2224/81211 , H01L2224/81801 , H01L2924/01006 , H01L2924/01019 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/351 , H01L2924/00
摘要: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a chip and a substrate. The method also includes bonding the chip to the substrate. The method also includes, after the bonding the chip, dispensing a sealing material between the chip and the substrate. In accordance with the method, the chip and the substrate are maintained within a temperature range from the bonding the chip to the dispensing the sealing material, and wherein a lower limit of the temperature range is approximately twice a room temperature.
摘要翻译: 本公开提供了制造半导体器件的方法。 该方法包括提供芯片和基板。 该方法还包括将芯片接合到衬底。 该方法还包括在粘合芯片之后,在芯片和基板之间分配密封材料。 根据该方法,将芯片和基板保持在从接合芯片到分配密封材料的温度范围内,并且其中温度范围的下限约为室温的两倍。
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公开(公告)号:US20130256874A1
公开(公告)日:2013-10-03
申请号:US13559840
申请日:2012-07-27
申请人: Yen-Liang Lin , Chen-Shien Chen , Tin-Hao Kuo , Sheng-Yu Wu , Tsung-Shu Lin , Chang-Chia Huang
发明人: Yen-Liang Lin , Chen-Shien Chen , Tin-Hao Kuo , Sheng-Yu Wu , Tsung-Shu Lin , Chang-Chia Huang
IPC分类号: H01L23/498
CPC分类号: H01L23/3192 , H01L23/293 , H01L23/49811 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05005 , H01L2224/05015 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05166 , H01L2224/05541 , H01L2224/05555 , H01L2224/05572 , H01L2224/05582 , H01L2224/05647 , H01L2224/13012 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2924/00014 , H01L2924/01029 , H01L2924/00012 , H01L2924/206 , H01L2924/01047
摘要: A device includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. The passivation layer has a first opening overlapping the metal pad, wherein the first opening has a first lateral dimension measured in a direction parallel to a major surface of the substrate. A polymer layer is over the passivation layer and covering the edge portions of the metal pad. The polymer layer has a second opening overlapping the metal pad. The second opening has a second lateral dimension measured in the direction. The first lateral dimension is greater than the second lateral dimension by more than about 7 μm. A Under-Bump metallurgy (UBM) includes a first portion in the second opening, and a second portion overlying portions of the polymer layer.
摘要翻译: 一种器件包括衬底,衬底上的金属焊盘以及覆盖金属焊盘的边缘部分的钝化层。 钝化层具有与金属焊盘重叠的第一开口,其中第一开口具有在平行于衬底的主表面的方向上测量的第一横向尺寸。 聚合物层在钝化层上方并覆盖金属焊盘的边缘部分。 聚合物层具有与金属垫重叠的第二开口。 第二开口具有在该方向上测量的第二横向尺寸。 第一横向尺寸大于第二横向尺寸大于约7μm。 下冲击冶金(UBM)包括第二开口中的第一部分和覆盖聚合物层部分的第二部分。
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公开(公告)号:US08922006B2
公开(公告)日:2014-12-30
申请号:US13559840
申请日:2012-07-27
申请人: Yen-Liang Lin , Chen-Shien Chen , Tin-Hao Kuo , Sheng-Yu Wu , Tsung-Shu Lin , Chang-Chia Huang
发明人: Yen-Liang Lin , Chen-Shien Chen , Tin-Hao Kuo , Sheng-Yu Wu , Tsung-Shu Lin , Chang-Chia Huang
IPC分类号: H01L23/488
CPC分类号: H01L23/3192 , H01L23/293 , H01L23/49811 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05005 , H01L2224/05015 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05166 , H01L2224/05541 , H01L2224/05555 , H01L2224/05572 , H01L2224/05582 , H01L2224/05647 , H01L2224/13012 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2924/00014 , H01L2924/01029 , H01L2924/00012 , H01L2924/206 , H01L2924/01047
摘要: A device includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. The passivation layer has a first opening overlapping the metal pad, wherein the first opening has a first lateral dimension measured in a direction parallel to a major surface of the substrate. A polymer layer is over the passivation layer and covering the edge portions of the metal pad. The polymer layer has a second opening overlapping the metal pad. The second opening has a second lateral dimension measured in the direction. The first lateral dimension is greater than the second lateral dimension by more than about 7 μm. A Under-Bump metallurgy (UBM) includes a first portion in the second opening, and a second portion overlying portions of the polymer layer.
摘要翻译: 一种器件包括衬底,衬底上的金属焊盘以及覆盖金属焊盘的边缘部分的钝化层。 钝化层具有与金属焊盘重叠的第一开口,其中第一开口具有在平行于衬底的主表面的方向上测量的第一横向尺寸。 聚合物层在钝化层上方并覆盖金属焊盘的边缘部分。 聚合物层具有与金属垫重叠的第二开口。 第二开口具有在该方向上测量的第二横向尺寸。 第一横向尺寸大于第二横向尺寸大于约7μm。 下冲击冶金(UBM)包括第二开口中的第一部分和覆盖聚合物层部分的第二部分。
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公开(公告)号:US08598030B2
公开(公告)日:2013-12-03
申请号:US12855360
申请日:2010-08-12
申请人: Chen-Cheng Kuo , Chen-Shien Chen
发明人: Chen-Cheng Kuo , Chen-Shien Chen
IPC分类号: H01L21/44
CPC分类号: H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05166 , H01L2224/05181 , H01L2224/05572 , H01L2224/05647 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/11472 , H01L2224/11474 , H01L2224/11849 , H01L2224/11902 , H01L2224/13017 , H01L2224/13018 , H01L2224/13022 , H01L2224/1308 , H01L2224/13083 , H01L2224/13099 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2924/00013 , H01L2924/00014 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01061 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/351 , H01L2924/01083 , H01L2924/01051 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552
摘要: A process for making a copper post with footing profile employs dual photoresist films of different photosensitivities and thicknesses on an under-bump-metallurgy (UBM) layer. After an exposure lithography process, a first opening with a substantially vertical sidewall is formed in a first photoresist film, and a second opening with a sloped sidewall is formed in a second photoresist film. The second opening has a top diameter and a bottom diameter greater than the top diameter, and the bottom diameter is greater than the diameter of the first opening. A conductive layer is then formed in the first opening and the second opening followed by removing the dual photoresist films.
摘要翻译: 用于制造具有基脚轮廓的铜柱的方法使用在凸块下 - 冶金(UBM)层上具有不同光敏度和厚度的双光致抗蚀剂膜。 在曝光光刻工艺之后,在第一光致抗蚀剂膜中形成具有基本上垂直的侧壁的第一开口,并且在第二光致抗蚀剂膜中形成具有倾斜侧壁的第二开口。 第二开口具有大于顶部直径的顶部直径和底部直径,并且底部直径大于第一开口的直径。 然后在第一开口和第二开口中形成导电层,随后除去双光致抗蚀剂膜。
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公开(公告)号:US08202800B2
公开(公告)日:2012-06-19
申请号:US13112347
申请日:2011-05-20
申请人: Chih-Hua Chen , Chen-Shien Chen , Chen-Cheng Kuo , Wen-Wei Shen
发明人: Chih-Hua Chen , Chen-Shien Chen , Chen-Cheng Kuo , Wen-Wei Shen
IPC分类号: H01L21/44
CPC分类号: H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要: A method of forming a through silicon via (TSV) structure includes forming an interconnect pad over a substrate. An under layer is formed over the interconnect pad. A vertical conductive post is formed at least partially through the substrate. At least one dummy structure is formed at least partially through the under layer. A top pad is formed over the dummy structure and the vertical conductive post. The top pad covers a wider area than a cross section of the vertical conductive post. The interconnect pad is electrically connected to the top pad. The dummy structure connects the top pad and the under layer thereby fastening the top pad and the interconnect pad.
摘要翻译: 形成贯穿硅通孔(TSV)结构的方法包括在衬底上形成互连焊盘。 在互连焊盘上形成下层。 至少部分地穿过衬底形成垂直导电柱。 至少部分地通过底层形成至少一个虚拟结构。 顶部衬垫形成在虚拟结构和垂直导电柱上。 顶部焊盘覆盖比垂直导电柱的横截面更宽的区域。 互连焊盘电连接到顶部焊盘。 虚拟结构连接顶部焊盘和下层,从而紧固顶部焊盘和互连焊盘。
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