公开(公告)号：US20110247210A1

公开(公告)日：2011-10-13

申请号：US13140637

申请日：2009-12-18

Applicant: Christian Val ,  Pascal Couderc ,  Alexandre Val

Inventor： Christian Val ,  Pascal Couderc ,  Alexandre Val

IPC: H05K3/30

CPC classification number: H01L21/6835 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/96 ,  H01L2221/68377 ,  H01L2224/04105 ,  H01L2224/13139 ,  H01L2224/16 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/81201 ,  H01L2224/81801 ,  H01L2224/838 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/141 ,  H05K1/185 ,  H05K3/321 ,  H05K2203/1469 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/0401

Abstract: A process for the wafer-scale fabrication of CMS electronic modules starts from a wafer with metallized outputs, comprising electronic components molded in resin and, on one side, the external outputs of the electronic components on which a nonoxidizable metal or alloy is deposited, and of a printed circuit provided with oxidizable metal or alloy contact pads. In the process, the wafer is cut in predetermined patterns for obtaining reconfigured molded components that include at least one electronic component; the reconfigured components are assembled on the printed circuit, the metallized external outputs of the reconfigured components being placed opposite the metallized contact pads of the printed circuit; and these external outputs are connected solderlessly to the metallized contact pads of the printed circuit by means of a material based on an electrically conductive adhesive or ink.

Abstract translation: 用于晶片尺寸制造CMS电子模块的工艺从具有金属化输出的晶片开始，包括以树脂模制的电子部件，以及在一侧上沉积有不可氧化的金属或合金的电子部件的外部输出，以及 设置有可氧化金属或合金接触垫的印刷电路。 在该过程中，以预定图案切割晶片以获得包括至少一个电子部件的重新配置的模制部件; 重新配置的组件被组装在印刷电路上，重新配置的组件的金属化的外部输出与印刷电路的金属化接触焊盘相对放置; 并且这些外部输出通过基于导电粘合剂或墨水的材料无焊地连接到印刷电路的金属化接触焊盘。

公开(公告)号：US07476965B2

公开(公告)日：2009-01-13

申请号：US11575751

申请日：2005-09-07

Applicant: Christian Val ,  Olivier Lignier ,  Regis Bocage

Inventor： Christian Val ,  Olivier Lignier ,  Regis Bocage

IPC: H01L23/48

CPC classification number: H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0201 ,  H05K1/111 ,  H05K1/112 ,  H05K3/4641 ,  H05K2201/09718 ,  H05K2201/09745 ,  H05K2201/09781 ,  H05K2203/165 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention relates to an electronic device incorporating a heat distributor. It applies more particularly to devices of the plastic package type, with one or more levels of components. According to the invention, the electronic device, for example of the package type, is provided for its external connection with pads distributed over a connection surface. It includes a thermally conducting plate lying parallel to said connection surface and having a nonuniform structure making it possible, when the device is exposed to a given external temperature, to supply a controlled amount of heat to each external connection pad according to its position on the connection surface. If the device is a package comprising a support of the printed circuit type, the conducting plate will advantageously form an internal layer of said support.

Abstract translation: 本发明涉及一种并入热分配器的电子设备。 它更具体地应用于塑料封装类型的器件，具有一个或多个级别的部件。 根据本发明，提供了例如封装类型的电子设备，用于其与分布在连接表面上的焊盘的外部连接。 它包括平行于所述连接表面并且具有不均匀结构的导热板，使得当设备暴露于给定的外部温度时，可以根据其在位置上的位置向每个外部连接垫提供受控量的热量 连接面。 如果设备是包括印刷电路类型的支撑体的封装，导电板将有利地形成所述支撑件的内层。

公开(公告)号：US20080289174A1

公开(公告)日：2008-11-27

申请号：US12158125

申请日：2006-12-19

Applicant: Christian Val

Inventor： Christian Val

IPC: H05K3/36

CPC classification number: H01L23/3107 ,  H01L25/105 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/49146 ,  Y10T29/49165 ,  Y10T29/49169 ,  H01L2924/00

Abstract: The invention relates to the collective fabrication of n 3D modules. It comprises a step of fabricating a batch of n wafers I on one and the same plate, this step being repeated K times, then a step of stacking the K plates, a step of forming plated-through holes in the thickness of the stack, these holes being intended for connecting the slices together, and then a step of cutting the stack in order to obtain the n 3D modules.The plate 10, which comprises silicon, is covered on one face 11 with an electrically insulating layer forming the insulating substrate. This face has grooves 20 that define n geometrical features, which are provided with an electronic component 1 connected to electrical connection pads 2′ placed on said face.After the stacking operation, holes are drilled perpendicular to the faces of the plates vertically in line with the grooves. The size of the holes is smaller than that of the grooves so that the silicon of each wafer 10 is isolated from the wall of the hole by resin.

Abstract translation: 本发明涉及n个3D模块的集体制作。 它包括在同一板上制造一批n个晶片I的步骤，该步骤重复K次，然后是堆叠K板的步骤，形成厚度为叠层的电镀通孔的步骤， 这些孔旨在将切片连接在一起，然后切割堆叠以获得n个3D模块的步骤。 包含硅的板10被覆盖在一个表面11上，其中形成绝缘基板的电绝缘层。 该面具有限定n个几何特征的槽20，其具有连接到放置在所述面上的电连接焊盘2'的电子部件1。 在堆叠操作之后，垂直于板的表面垂直钻孔，与槽一致。 孔的尺寸小于槽的尺寸，使得每个晶片10的硅通过树脂与孔的壁隔离。

公开(公告)号：US5640760A

公开(公告)日：1997-06-24

申请号：US437797

申请日：1995-05-09

Applicant: Christian Val ,  Andre Gerard

Inventor： Christian Val ,  Andre Gerard

IPC: H01L25/00 ,  H01L21/98 ,  H01L23/538 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00 ,  H05K3/28 ,  H05K3/30 ,  H05K3/36

CPC classification number: H01L25/50 ,  H01L25/105 ,  H05K3/284 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2924/0002 ,  H05K1/144 ,  H05K1/181 ,  H05K1/182 ,  H05K2203/0235 ,  H05K2203/1316 ,  H05K2203/1469 ,  H05K3/0097 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49798

Abstract: In a method for the interconnection of stacked packages, each of the packages encapsulating, for example, a semiconductor chip containing an integrated circuit, a memory for example, the packages provided with pins are mounted on a printed circuit board. The printed circuit boards are stacked and fixedly joined with one another by means of a coating, for example a resin coating. The stack is sliced through so as to form bars, the pins of the packages being electrically connected to the side surfaces of the bars by means of the tracks of the printed circuit boards. The connection of the packages to one another is done on the side faces of the bars. The bars are then sliced through to obtain unit blocks of stacked packages.

Abstract translation: 在堆叠封装互连的方法中，封装例如包含集成电路的半导体芯片，例如存储器，具有引脚的封装的每个封装安装在印刷电路板上。 印刷电路板通过涂层（例如树脂涂层）堆叠并彼此固定地接合。 堆叠被切片以形成条，封装的引脚通过印刷电路板的轨道电连接到条的侧表面。 包装件彼此的连接在条的侧面上完成。 然后将条切片通过以获得堆叠包装的单元块。

公开(公告)号：US4755910A

公开(公告)日：1988-07-05

申请号：US942655

申请日：1986-12-17

Applicant: Christian Val

Inventor： Christian Val

IPC: H01L23/057 ,  H01L23/538 ,  H01L23/64 ,  H01L25/065 ,  H01L25/16 ,  H05K7/06

CPC classification number: H01L25/16 ,  H01L23/057 ,  H01L23/5383 ,  H01L23/642 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H01L2924/1627 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  Y10S257/916

Abstract: A housing more particularly intended for encapsulating a wafer scale electronic circuit, realized in hybrid technology or integrated on semi-conducting substrate. In this housing:supply voltages are brought to different points disposed over the surface of the circuitlead-in circuits are constituted by conducting planes, placed in superimposed layers in the cover or the base of the housing.

Abstract translation: 更具体地，用于封装晶片级电子电路的壳体，其在混合技术中实现或集成在半导体衬底上。 在这种外壳中：电源电压被带到设置在电路表面上的不同点，引入电路由导电平面构成，放置在叠层中，盖子或壳体的底部。

公开(公告)号：US4546028A

公开(公告)日：1985-10-08

申请号：US487153

申请日：1983-04-21

Applicant: Christian Val

Inventor： Christian Val

IPC: H01B17/60 ,  H01L23/14 ,  H01L23/373 ,  B32B3/12

CPC classification number: H01L23/142 ,  H01L23/3731 ,  H01L23/3733 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01025 ,  H01L2924/01057 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/16152 ,  Y10T428/24149

Abstract: A composite substrate, electrically insulating and with high heat conduction, for semiconductor circuits housing. It comprises principally an electrically insulating material such as alumina, in the form of a honeycombed wafer with cells, and a heat conducting material placed in said cells, such as a metal.

Abstract translation: 一种用于半导体电路壳体的电绝缘并具有高热传导性的复合衬底。 其主要包括电绝缘材料如氧化铝，其具有带有电池的蜂窝状晶片的形式，以及放置在所述电池中的导热材料，例如金属。

公开(公告)号：US4408256A

公开(公告)日：1983-10-04

申请号：US346907

申请日：1982-02-08

Applicant: Christian Val

Inventor： Christian Val

IPC: H01L23/057 ,  H01L23/15 ,  H01L23/64 ,  H01L25/16 ,  H05K1/03 ,  H05K1/16 ,  H05K3/40 ,  H05K7/02

CPC classification number: H01L23/057 ,  H01L23/15 ,  H01L23/642 ,  H01L25/165 ,  H05K1/162 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/0306 ,  H05K2201/09672 ,  H05K3/403

Abstract: The invention relates to microboxes for encapsulating electronic circuits.Electronic circuits frequently comprise decoupling capacitors or the like, which occupy a large amount of space compared with the integrated parts of the box. The invention provides for the use of the bottom or substrate of the encapsulating box as capacitors after metallizing the two faces. The dielectric material is matched to the desired capacitance values. The microbox substrate is formed by a multilayer capacitor for high values.

Abstract translation: 本发明涉及用于封装电子电路的微盒。 电子电路经常包括去耦电容器等，与盒的集成部分相比占用了大量的空间。 本发明提供了在将两个表面金属化之后使用封装盒的底部或基底作为电容器。 电介质材料与期望的电容值相匹配。 微型盒基板由用于高值的多层电容器形成。

公开(公告)号：US07951649B2

公开(公告)日：2011-05-31

申请号：US12438179

申请日：2007-08-03

Applicant: Christian Val

Inventor： Christian Val

IPC: H01L21/50

CPC classification number: H01L22/32 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2221/68386 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/1461 ,  Y10T29/49004 ,  H01L2924/00

Abstract: The invention relates to the collective fabrication of n 3D module. It comprises a step of fabricating a batch of n dies i at one and the same thin plane wafer (10) of thickness es comprising silicon, covered on one face with electrical connection pads (20), called test pads, and then with a thin electrically insulating layer (4) of thickness ei, forming the insulating substrate provided with at least one silicon electronic component (11) having connection pads (2) connected to the test pads (20) through the insulating layer. The components are encapsulated in an insulating resin (6) of thickness er, filling the spaces between the components, then separated from one another by first grooves (30) with a width L1 and a depth P1 such that ei+er

公开(公告)号：US07877874B2

公开(公告)日：2011-02-01

申请号：US12158125

申请日：2006-12-19

Applicant: Christian Val

Inventor： Christian Val

IPC: H01K3/10

CPC classification number: H01L23/3107 ,  H01L25/105 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/49146 ,  Y10T29/49165 ,  Y10T29/49169 ,  H01L2924/00

Abstract: The invention relates to the collective fabrication of n 3D modules. A batch of n wafers I are fabricated on one and the same plate. This step is repeated K times. The K plates are stacked. Plated-through holes are formed in the thickness of the stack. These holes are intended for connecting the slices together. The stack is cut in order to obtain the n 3D modules. The plate 10, which comprises silicon, is covered on one face 11 with an electrically insulating layer forming the insulating substrate. This face has grooves 20 that define n geometrical features, which are provided with an electronic component 1 connected to electrical connection pads 2′ placed on said face.

Abstract translation: 本发明涉及n个3D模块的集体制作。 一批n个晶片I被制造在同一个板上。 这一步重复K次。 K盘堆放。 电镀通孔形成在堆叠的厚度上。 这些孔用于将切片连接在一起。 切割堆叠以获得n个3D模块。 包含硅的板10被覆盖在一个表面11上，其中形成绝缘基板的电绝缘层。 该面具有限定n个几何特征的槽20，其具有连接到放置在所述面上的电连接焊盘2'的电子部件1。

公开(公告)号：US07635639B2

公开(公告)日：2009-12-22

申请号：US10562685

申请日：2004-06-30

Applicant: Christian Val ,  Olivier Lignier

Inventor： Christian Val ,  Olivier Lignier

IPC: H01L21/46

CPC classification number: H01L24/85 ,  H01G4/228 ,  H01G4/40 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A method for interconnecting active and passive components in two or three dimensions, and the resulting thin heterogeneous components. The method comprises: positioning and fixing (11) at least one active component and one passive component on a flat support (23), the terminals being in contact with the support, depositing (12) a polymer layer (24) on all of the support and the components, removing the support (14), redistributing the terminals (15) between the components and/or toward the periphery by metal conductors (26) arranged in a predetermined layout, making it possible to obtain a heterogeneous reconstituted structure, heterogeneously thinning (16) the structure by nonselective surface treatment of the polymer layer and at least one passive component (22).

Abstract translation: 一种用于将两个或三个维度的主动和被动部件互相连接的方法，以及所得到的薄异质部件。 该方法包括：在平坦支撑件（23）上定位和固定（11）至少一个有源部件和一个无源部件，所述端子与支撑件接触，在所有的所有端子上沉积（12）聚合物层（24） 支撑件和部件，去除支撑件（14），通过以预定布局布置的金属导体（26）将部件之间的端子（15）重新分配和/或朝向周边，使得可以非均匀地获得非均匀的重构结构 通过聚合物层和至少一个无源部件（22）的非选择性表面处理来使结构变薄（16）。