公开(公告)号：US20160064382A1

公开(公告)日：2016-03-03

申请号：US14475720

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Stefan Flachowsky ,  Gerd Zschätzsch

IPC: H01L27/092 ,  H01L29/49 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/308 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/28097 ,  H01L21/3083 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4941 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

Abstract: The present disclosure provides a method of forming a semiconductor device structure with selectively fabricating semiconductor device structures having fully silicided (FuSi) gates and partially silicided gates. In aspects of the present disclosure, a semiconductor device structure with a first semiconductor device and a second semiconductor device is provided, wherein each of the first and second semiconductor devices includes a gate structure over an active region, each of the gate structures having a gate electrode material and a gate dielectric material. The gate electrode material of the first semiconductor device is recessed, resulting in a recessed first gate electrode material which is fully silicided during a subsequent silicidation process. On the gate electrode material of the second semiconductor device, a silicide portion is formed during the silicidation process.

Abstract translation: 本公开提供了一种形成半导体器件结构的方法，其选择性地制造具有完全硅化（FuSi）栅极和部分硅化栅极的半导体器件结构。 在本公开的方面中，提供了具有第一半导体器件和第二半导体器件的半导体器件结构，其中第一和第二半导体器件中的每一个在有源区域上包括栅极结构，每个栅极结构具有栅极 电极材料和栅极电介质材料。 第一半导体器件的栅电极材料凹陷，导致凹陷的第一栅电极材料，其在随后的硅化工艺期间被完全硅化。 在第二半导体器件的栅极电极材料上，在硅化处理期间形成硅化物部分。

公开(公告)号：US09214396B1

公开(公告)日：2015-12-15

申请号：US14294467

申请日：2014-06-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Gerd Zschaetzsch

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/45 ,  H01L21/285 ,  H01L21/265

CPC classification number: H01L21/823814 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/823412 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of forming a transistor device is provided, including the subsequently performed steps of forming a gate electrode on a first semiconductor layer, forming an interlayer dielectric over the gate electrode and the first semiconductor layer, forming a first opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on one side of the gate electrode and a second opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on another side of the gate electrode, the first and second openings reaching to the first semiconductor layer, forming cavities in the first semiconductor layer through the first and second openings formed in the interlayer dielectric, and forming embedded second semiconductor layers in the cavities.

Abstract translation: 提供了一种形成晶体管器件的方法，包括随后执行的步骤，在第一半导体层上形成栅电极，在栅电极和第一半导体层上形成层间电介质，在层间电介质中形成第一开口 在栅电极的一侧上与栅电极横向间隔开的预定距离，并且在栅极电极的另一侧与栅电极横向间隔开预定距离的层间电介质中的第二开口，第一和第二开口到达第一 半导体层，通过形成在层间电介质中的第一和第二开口在第一半导体层中形成空腔，以及在空腔中形成嵌入的第二半导体层。

公开(公告)号：US20150340380A1

公开(公告)日：2015-11-26

申请号：US14817734

申请日：2015-08-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Matthias Kessler ,  Jan Hoentschel

IPC: H01L27/12 ,  H01L29/94 ,  H01L29/06 ,  H01L29/778 ,  H01L29/16 ,  H01L29/20 ,  H01L29/861 ,  H01L29/78

CPC classification number: H01L21/84 ,  H01L21/02428 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823878 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66181 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/861 ,  H01L29/945

Abstract: A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate.

Abstract translation: 一种结构包括半导体衬底，绝缘体上半导体区域和体区域。 绝缘体上半导体区域包括第一半导体区域，设置在半导体衬底和第一半导体区域之间的电介质层，以及包括设置在第一半导体区域中的有源区的第一晶体管。 电介质层在第一半导体区域和半导体衬底之间提供电隔离。 本体区域包括直接设置在半导体衬底上的第二半导体区域。

公开(公告)号：US20150340362A1

公开(公告)日：2015-11-26

申请号：US14819646

申请日：2015-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Martin Gerhardt ,  Stefan Flachowsky ,  Matthias Kessler

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/088 ,  H01L21/28202 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833

Abstract: An integrated circuit product includes first and second transistors positioned in and above first and second active regions. The first transistor has a first gate length and a first gate material stack that includes a first gate dielectric layer having a first thickness and at least one layer of metal positioned above the first gate dielectric layer, the first gate dielectric layer including a layer of a first high-k insulating material and a layer of a second high-k insulating material positioned on the layer of the first high-k insulating material. The second transistor has a second gate length and a second gate material stack that includes a second gate dielectric layer having a second thickness positioned above the second active region and at least one layer of metal positioned above the second gate dielectric layer, the second gate dielectric layer including a layer of the second high-k insulating material.

Abstract translation: 集成电路产品包括位于第一和第二有源区域中和之上的第一和第二晶体管。 第一晶体管具有第一栅极长度和第一栅极材料堆叠，其包括具有第一厚度的第一栅极电介质层和位于第一栅极介电层上方的至少一层金属，第一栅极介电层包括一层 第一高k绝缘材料和位于第一高k绝缘材料层上的第二高k绝缘材料层。 第二晶体管具有第二栅极长度和第二栅极材料堆叠，其包括具有位于第二有源区上方的第二厚度的第二栅极介电层和位于第二栅极介电层上方的至少一层金属，第二栅极电介质 层包括第二高k绝缘材料层。

公开(公告)号：US20150333057A1

公开(公告)日：2015-11-19

申请号：US14276515

申请日：2014-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Andreas Kurz ,  Sven Beyer ,  Wolfgang Buchholtz

IPC: H01L27/07 ,  H01L49/02

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/0738 ,  H01L28/20 ,  H01L29/66545

Abstract: The present disclosure relates to a semiconductor structure comprising a resistor, at least part of the resistor forming a meandering shape in a vertical direction with respect to a substrate of the semiconductor structure. The disclosure further relates to a semiconductor manufacturing process comprising a step for realizing at least one first fin, and a step for realizing a resistor comprising a meandering shape in a vertical direction based on the at least one first fin.

Abstract translation: 本公开涉及包括电阻器的半导体结构，所述电阻器的至少一部分相对于半导体结构的衬底在垂直方向上形成曲折形状。 本发明还涉及包括用于实现至少一个第一鳍的步骤的半导体制造工艺，以及基于至少一个第一鳍实现在垂直方向上包括曲折形状的电阻的步骤。

公开(公告)号：US09129843B1

公开(公告)日：2015-09-08

申请号：US14302880

申请日：2014-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Richter ,  Peter Javorka ,  Jan Hoentschel

IPC: H01F17/00 ,  H01L49/02 ,  H01L21/263 ,  H01L21/762 ,  H01L27/06 ,  H01L29/06 ,  B23K26/00 ,  B23K26/38

CPC classification number: H01L28/10 ,  B23K26/38 ,  B23K26/53 ,  H01L21/263 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/32155 ,  H01L21/76224 ,  H01L27/0617 ,  H01L29/0653 ,  H01L29/66083 ,  H01L29/665 ,  H01L29/78 ,  H01L29/86

Abstract: A method of forming an inductor in a crystal semiconductor layer is provided, including generating an ion beam, directing the ion beam to a surface of the crystal semiconductor layer, applying a magnetic field to the ion beam to generate a helical motion of the ions and forming a three-dimensional helical structure in the crystal semiconductor layer by means of the ions of the ion beam.

Abstract translation: 提供一种在晶体半导体层中形成电感器的方法，包括产生离子束，将离子束引导到晶体半导体层的表面，向离子束施加磁场以产生离子的螺旋运动，以及 通过离子束的离子在晶体半导体层中形成三维螺旋结构。

公开(公告)号：US20150214121A1

公开(公告)日：2015-07-30

申请号：US14677503

申请日：2015-04-02

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ralf Illgen ,  Stefan Flachowsky

IPC: H01L21/84 ,  H01L21/324 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L21/3213 ,  H01L29/161 ,  H01L29/78 ,  H01L29/167 ,  H01L21/28 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/16

CPC classification number: H01L21/84 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02636 ,  H01L21/28035 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1203 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/51 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78696

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing an ultrathin body fully depleted silicon-on-insulator substrate. The method forms a temporary gate structure over the substrate and forms lightly doped source/drain extension areas around the gate structure. Further, the method includes performing an annealing process on the lightly doped source/drain extension areas. Outdiffusion from the lightly doped source/drain extensions is less than 5 nm during the annealing process. The method includes forming a strain region around the gate structure.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供绝缘体上绝缘体上的绝缘体上的超薄体。 该方法在衬底上形成临时栅极结构，并在栅极结构周围形成轻掺杂的源极/漏极延伸区域。 此外，该方法包括对轻掺杂源极/漏极延伸区域进行退火处理。 在退火过程中，轻掺杂源极/漏极扩展部分的扩散不足5nm。 该方法包括在栅极结构周围形成应变区域。

公开(公告)号：US20150129964A1

公开(公告)日：2015-05-14

申请号：US14469741

申请日：2014-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tim Baldauf ,  Stefan Flachowsky

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/068 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0676 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/7827 ,  H01L29/785

Abstract: A semiconductor device is provided including a semiconductor substrate and a nanowire formed over the semiconductor substrate and wherein the nanowire includes a first layer exhibiting tensile stress and a second layer exhibiting compressive stress.

Abstract translation: 提供了半导体器件，其包括形成在半导体衬底上的半导体衬底和纳米线，并且其中纳米线包括呈现拉伸应力的第一层和呈现压应力的第二层。

公开(公告)号：US20150111349A1

公开(公告)日：2015-04-23

申请号：US14579255

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Matthias Kessler ,  Jan Hoentschel

IPC: H01L21/84 ,  H01L21/8234

CPC classification number: H01L21/84 ,  H01L21/02428 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823878 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66181 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/861 ,  H01L29/945

Abstract: A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate.

Abstract translation: 一种结构包括半导体衬底，绝缘体上半导体区域和体区域。 绝缘体上半导体区域包括第一半导体区域，设置在半导体衬底和第一半导体区域之间的电介质层，以及包括设置在第一半导体区域中的有源区的第一晶体管。 电介质层在第一半导体区域和半导体衬底之间提供电隔离。 本体区域包括直接设置在半导体衬底上的第二半导体区域。

公开(公告)号：US20150050787A1

公开(公告)日：2015-02-19

申请号：US13965860

申请日：2013-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Gerd Zschaetzsch ,  Jan Hoentschel

IPC: H01L29/66

CPC classification number: H01L21/28097 ,  H01L21/8238 ,  H01L21/823835 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/6659

Abstract: When forming field-effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art, which may overcome this problem. However, formation of a fully silicided gate is hindered by the fact that silicidation of the source and drain regions and of the gate electrode are normally performed simultaneously. The claimed method proposes two consecutive silicidation processes which are decoupled with respect to each other. During the first silicidation process, a metal silicide is formed forming an interface with the source and drain regions and without affecting the gate electrode. During the second silicidation, a metal silicide layer having an interface with the gate electrode is formed, without affecting the transistor source and drain regions.

Abstract translation: 当形成场效应晶体管时，常见的问题是在栅电极中的金属薄膜与其上形成的半导体材料（通常为多晶硅）之间的界面处形成肖特基势垒。 完全硅化的门在现有技术中是已知的，这可以克服这个问题。 然而，完全硅化的栅极的形成受到源极和漏极区域以及栅极电极的硅化同时正常执行的事实的阻碍。 所要求保护的方法提出了两个相互连接的硅化过程。 在第一硅化工艺期间，形成金属硅化物，形成与源区和漏区的界面，而不影响栅电极。 在第二硅化处理期间，形成与栅电极具有界面的金属硅化物层，而不会影响晶体管的源极和漏极区域。