公开(公告)号：US20240186251A1

公开(公告)日：2024-06-06

申请号：US18075360

申请日：2022-12-05

Applicant: Intel Corporation

Inventor： Minglu LIU ,  YANG WU ,  Yuting WANG ,  Lawrence ROSS ,  Mine KAYA ,  Gang DUAN ,  Edvin CETEGEN ,  Alexander AGUINAGA

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/13 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/13 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/81203 ,  H01L2924/351

Abstract: Embodiments disclosed herein include package architectures. In an embodiment, the package architecture comprises a package substrate, a first bridge in the package substrate, where the first bridge includes conductive routing, and a second bridge in the package substrate. In an embodiment, the package architecture further comprises a third bridge in the package substrate, where the second bridge and the third bridge are positioned symmetrically about the first bridge.

公开(公告)号：US20240071883A1

公开(公告)日：2024-02-29

申请号：US17893893

申请日：2022-08-23

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Sashi S. KANDANUR ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Jeremy D. ECTON

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/544

CPC classification number: H01L23/49827 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments disclosed herein include cores for package substrates. In an embodiment, the core comprises a first substrate, where the first substrate comprises glass. In an embodiment, the core further comprises a first through glass via (TGV) through the first substrate and a second substrate, where the second substrate comprises glass. In an embodiment, the core further comprises a second TGV through the second substrate, where the first TGV is aligned with the second TGV.

公开(公告)号：US20240055345A1

公开(公告)日：2024-02-15

申请号：US17886278

申请日：2022-08-11

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON ,  Rahul N. MANEPALLI

IPC: H01L23/522 ,  H01L49/02 ,  H01G11/70 ,  H01L23/15

CPC classification number: H01L23/5223 ,  H01L28/40 ,  H01G11/70 ,  H01L23/15

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate, where the substrate comprises glass. In an embodiment, a pillar is over the substrate, and a capacitor is over the pillar. In an embodiment, the capacitor comprises a first conductive layer on the pillar, a dielectric layer over the first conductive layer, and a second conductive layer over the dielectric layer.

公开(公告)号：US20230361044A1

公开(公告)日：2023-11-09

申请号：US18224794

申请日：2023-07-21

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Rahul MANEPALLI ,  Gang DUAN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5381 ,  H01L23/5386 ,  H01L23/3107 ,  H01L23/562 ,  H01L25/0652 ,  H01L25/50 ,  H01L21/6835 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/5384 ,  H01L2225/06589 ,  H01L2221/68372 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06582

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

公开(公告)号：US20230343774A1

公开(公告)日：2023-10-26

申请号：US18216275

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Gang DUAN ,  Deepak KULKARNI

IPC: H01L23/538 ,  H01L23/29 ,  H01L21/683 ,  H01L25/00 ,  H01L23/48 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5389 ,  H01L2221/68309 ,  H01L2221/68345 ,  H01L2221/68359

Abstract: Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.

公开(公告)号：US20230086920A1

公开(公告)日：2023-03-23

申请号：US17481245

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Liang HE ,  Jisu JIANG ,  Jung Kyu HAN ,  Gang DUAN ,  Yosuke KANAOKA ,  Jason M. GAMBA ,  Bai NIE ,  Robert Alan MAY ,  Kimberly A. DEVINE ,  Mitchell ARMSTRONG ,  Yue DENG

IPC: H01L23/31 ,  H01L23/22

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques for a dam structure on a substrate that is proximate to a die coupled with the substrate, where the dam decreases the risk of die shift during encapsulation material flow over the die during the manufacturing process. The dam structure may fully encircle the die. During encapsulation material flow, the dam structure creates a cavity that moderates the different flow rates of material that otherwise would exert different pressures the sides of the die and cause to die to shift its position on the substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20220115367A1

公开(公告)日：2022-04-14

申请号：US17556660

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Gang DUAN ,  Deepak KULKARNI

IPC: H01L25/00 ,  H01L23/48 ,  H01L23/538 ,  H01L23/29 ,  H01L21/683 ,  H01L23/31

Abstract: Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.

公开(公告)号：US20200343049A1

公开(公告)日：2020-10-29

申请号：US16392028

申请日：2019-04-23

Applicant: Intel Corporation

Inventor： Sameer PAITAL ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Kristof DARMAWIKARTA

IPC: H01G4/33 ,  H01L23/498 ,  H01L23/538 ,  H01G4/30 ,  H01G4/38 ,  H01G4/224 ,  H01L23/00

Abstract: Embodiments disclosed herein include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a package substrate, an organic layer over the package substrate, and a capacitor embedded in the organic layer. In an embodiment, the capacitor comprises, a first electrode, where the first electrode comprises a seam between a first conductive layer and a second conductive layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer.

公开(公告)号：US20200005990A1

公开(公告)日：2020-01-02

申请号：US16024721

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Sameer PAITAL ,  Srinivas PIETAMBARAM ,  Yonggang LI ,  Bai NIE ,  Kristof DARMAWIKARTA ,  Gang DUAN

IPC: H01F27/28 ,  H01F27/24 ,  H01L21/48 ,  H01L25/16 ,  H01L23/498 ,  H01F41/04 ,  H01L49/02

Abstract: Embodiments herein relate to systems, apparatuses, or processes for embedding a magnetic core or a magnetic inductor in a substrate layer by applying a copper layer to a portion of the substrate layer, creating a structure in the substrate layer on top of at least part of the copper layer to identify a defined region within the substrate layer, and inserting a magnetic paste into the defined region where the copper layer identifies a side of the defined region and where the structure is to contain the magnetic paste within the defined region while the magnetic paste cures.

公开(公告)号：US20250112164A1

公开(公告)日：2025-04-03

申请号：US18374932

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Onur OZKAN ,  Ryan CARRAZZONE ,  Rui ZHANG ,  Haobo CHEN ,  Ziyin LIN ,  Yiqun BAI ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Bin MU ,  Mohit GUPTA ,  Jeremy D. ECTON ,  Brandon C. MARIN ,  Xiaoying GUO ,  Steve S. CHO ,  Ali LEHAF ,  Venkata Rajesh SARANAM ,  Shripad GOKHALE ,  Kartik SRINIVASAN ,  Edvin CETEGEN ,  Mine KAYA ,  Nicholas S. HAEHN ,  Deniz TURAN

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

Abstract: A device comprises a substrate comprising a plurality of build-up layers and a cavity. A bridge die is located within the cavity and a plurality of cavity side bumps are on one side of the bridge die. A plurality of interconnect pads with variable heights are on one of the build-up layers of the substrate coupled to the plurality of the cavity side bumps to bond the bridge die to the substrate.