公开(公告)号：US20140357055A1

公开(公告)日：2014-12-04

申请号：US13903013

申请日：2013-05-28

Applicant: Infineon Technologies AG

Inventor： Anja Gissibl ,  Hermann Wendt ,  Thomas Fischer ,  Bernhard Weidgans ,  Gudrun Stranzl ,  Tobias Schmidt ,  Dietrich Bonart

IPC: H01L21/306 ,  H01L21/78 ,  H01L21/3065

CPC classification number: H01L21/78 ,  H01L21/28568 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/76841 ,  H01L21/76892

Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.

Abstract translation: 提供了一种用于处理半导体工件的方法，其可以包括：提供包括设置在半导体工件侧面的金属化层堆叠的半导体工件，金属化层堆叠包括至少第一层和设置在第一层上的第二层 层，其中所述第一层包含第一材料，并且所述第二层包含不同于所述第一材料的第二材料; 图案化金属化层堆叠，其中图案化金属化层堆叠包括通过蚀刻溶液湿法蚀刻第一层和第二层，蚀刻溶液对于第一材料和第二材料具有至少基本上相同的蚀刻速率。

公开(公告)号：US20140319689A1

公开(公告)日：2014-10-30

申请号：US14330988

申请日：2014-07-14

Applicant: Infineon Technologies AG

Inventor： Johann Gatterbauer ,  Bernhard Weidgans

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L21/563 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/94 ,  H01L2224/02166 ,  H01L2224/0219 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03614 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/0556 ,  H01L2224/05562 ,  H01L2224/05583 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/27334 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48472 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/01024 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad having lower sidewalls and upper sidewalls and reducing a lower width of each contact pad so that an upper width of each contact pad is larger than the lower width. The method further includes forming a photoresist over the plurality of contact pads and removing portions of the photoresist thereby forming sidewall spacers along the lower sidewalls.

Abstract translation: 公开了芯片接触焊盘和制造芯片接触焊盘的方法。 本发明的一个实施例包括在工件上形成多个接触垫，每个接触垫具有下侧壁和上侧壁，并减小每个接触垫的较低宽度，使得每个接触垫的上部宽度大于下部宽度 。 该方法还包括在多个接触焊盘上形成光致抗蚀剂并去除光致抗蚀剂的部分，从而沿着下侧壁形成侧壁间隔物。

公开(公告)号：US20140167224A1

公开(公告)日：2014-06-19

申请号：US13715922

申请日：2012-12-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Manfred Schneegans ,  Bernhard Weidgans ,  Franco Mariani ,  Alexander Heinrich

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/78 ,  H01L21/6836 ,  H01L23/3677 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L29/0657 ,  H01L29/45 ,  H01L2221/68327 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83191 ,  H01L2224/83365 ,  H01L2224/8382 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device includes a semiconductor chip including a first main face and a second main face. The second main face is the backside of the semiconductor chip. The second main face includes a first region and a second region. The second region is a peripheral region of the second main face and the level of the first region and the level of the second region are different. The first region may be filled with metal and may be planarized to the same level as the second region.

Abstract translation: 半导体器件包括具有第一主面和第二主面的半导体芯片。 第二主面是半导体芯片的背面。 第二主面包括第一区域和第二区域。 第二区域是第二主面的周边区域，第一区域的高度和第二区域的高度不同。 第一区域可以用金属填充，并且可以被平坦化到与第二区域相同的水平。

公开(公告)号：US20140117509A1

公开(公告)日：2014-05-01

申请号：US13661810

申请日：2012-10-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Manfred Schneegans ,  Juergen Foerster ,  Bernhard Weidgans ,  Norbert Urbansky ,  Tilo Rotth

IPC: H01L21/768 ,  C23C14/34 ,  H01L23/48 ,  H01L21/3205 ,  H01L29/06

CPC classification number: H01L21/2855 ,  C23C14/14 ,  C23C14/34 ,  C23C14/3414 ,  C23C14/3492 ,  C23C14/54 ,  H01L21/76877

Abstract: Various techniques, methods and devices are disclosed where metal is deposited on a substrate, and stress caused by the metal to the substrate is limited, for example to limit a bending of the wafer.

Abstract translation: 公开了各种技术，方法和装置，其中金属沉积在基板上，并且金属对基板引起的应力受到限制，例如限制晶片的弯曲。

公开(公告)号：US20220216173A1

公开(公告)日：2022-07-07

申请号：US17376372

申请日：2021-07-15

Applicant: Infineon Technologies AG

Inventor： Thomas Behrens ,  Alexander Heinrich ,  Evelyn Napetschnig ,  Bernhard Weidgans ,  Catharina Wille ,  Christina Yeong

IPC: H01L23/00 ,  B23K35/26 ,  C22C13/02

Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.

公开(公告)号：US11069644B2

公开(公告)日：2021-07-20

申请号：US16556823

申请日：2019-08-30

Applicant: Infineon Technologies AG

Inventor： Thomas Behrens ,  Alexander Heinrich ,  Evelyn Napetschnig ,  Bernhard Weidgans ,  Catharina Wille ,  Christina Yeong

IPC: H01L23/00 ,  B23K35/26 ,  C22C13/02

Abstract: A semiconductor device and method is disclosed. In one embodiment, the semiconductor device comprises a semiconductor die comprising a first surface and a second surface opposite to the first surface, a first metallization layer disposed on the first surface of the semiconductor die, a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, and a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body, wherein the first contact member is connected with the Ni-based layer to the first solder layer.

公开(公告)号：US10658309B2

公开(公告)日：2020-05-19

申请号：US16418006

申请日：2019-05-21

Applicant: Infineon Technologies AG

Inventor： Marianne Mataln ,  Michael Nelhiebel ,  Rainer Pelzer ,  Bernhard Weidgans

IPC: H01L23/00 ,  H01L23/58 ,  B81B7/00

Abstract: A semiconductor device includes a substrate, a structured interlayer on the substrate and having a defined edge, and a structured metallization on the structured interlayer and also having a defined edge. The defined edge of the structured interlayer faces the same direction as the defined edge of the structured metallization. The defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 0.5 microns so that the defined edge of the structured metallization terminates before reaching the defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature and the structured metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer.

公开(公告)号：US10651140B2

公开(公告)日：2020-05-12

申请号：US16101114

申请日：2018-08-10

Applicant: Infineon Technologies AG

Inventor： Manfred Schneegans ,  Franziska Haering ,  Hans-Joachim Schulze ,  Bernhard Weidgans

IPC: H01L21/44 ,  H01L23/00 ,  H01L29/417 ,  H01L29/40 ,  H01L23/532 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/739 ,  H01L21/768

Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor substrate that has a conductive structure, and forming a precursor auxiliary layer stack on a first section of the conductive structure. The precursor auxiliary layer stack has a precursor adhesion layer and a precursor barrier layer between the precursor adhesion layer and the conductive structure. The precursor adhesion layer contains a second metal. The method further includes forming, on the precursor auxiliary layer stack, a metal structure containing a first metal and forming, from portions of the precursor auxiliary layer stack an adhesive layer containing the first and second metals.

公开(公告)号：US10648096B2

公开(公告)日：2020-05-12

申请号：US14948463

申请日：2015-11-23

Applicant: Infineon Technologies AG

Inventor： Werner Robl ,  Michael Melzl ,  Manfred Schneegans ,  Bernhard Weidgans ,  Franziska Haering

IPC: C25D5/50 ,  C25D17/12 ,  C25D3/38 ,  C25D3/48 ,  C25D3/46 ,  C25D3/12 ,  C25D3/52 ,  C25D3/32 ,  C25D15/00 ,  C25D7/12 ,  H01L21/288 ,  H01L23/532

Abstract: An electrolyte may be provided. The electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100° C., and a water soluble metal salt, and the electrolyte may be free from carbon nanotubes. In various embodiments, a method of forming a metal layer may be provided: The method may include depositing a metal layer on a carrier using an electrolyte, wherein the electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100° C. and a water soluble metal salt, wherein the electrolyte is free from carbon nanotubes; and annealing the metal layer to form a metal layer comprising a plurality of pores. In various embodiments, a semiconductor device may be provided. The semiconductor device may include a metal layer including a plurality of pores, wherein the plurality of pores may be formed in the metal layer as remnants of an additive having resided in the plurality of pores and having at least partially decomposed or evaporated. To keep a high elasticity over a wide temperature range (up to 450° C.), an adhesion layer may stabilize the metal grain boundaries and may fix dislocation gliding inside metal grains. In various embodiments, a metal layer is provided. The metal layer may include a plurality of pores having ellipsoidal or spheroidal shape.

公开(公告)号：US20190273050A1

公开(公告)日：2019-09-05

申请号：US16418006

申请日：2019-05-21

Applicant: Infineon Technologies AG

Inventor： Marianne Mataln ,  Michael Nelhiebel ,  Rainer Pelzer ,  Bernhard Weidgans

IPC: H01L23/00

Abstract: A semiconductor device includes a substrate, a structured interlayer on the substrate and having a defined edge, and a structured metallization on the structured interlayer and also having a defined edge. The defined edge of the structured interlayer faces the same direction as the defined edge of the structured metallization. The defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 0.5 microns so that the defined edge of the structured metallization terminates before reaching the defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature and the structured metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer.