公开(公告)号：US09117828B2

公开(公告)日：2015-08-25

申请号：US12717573

申请日：2010-03-04

申请人： Weng-Jin Wu ,  Ku-Feng Yang ,  Wen-Chih Chiou

发明人： Weng-Jin Wu ,  Ku-Feng Yang ,  Wen-Chih Chiou

IPC分类号： H01L21/50 ,  H01L21/56 ,  H01L21/71 ,  H01L21/60 ,  H01L21/683 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L29/06

CPC分类号： H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3121 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L24/95 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method of handling a thin wafer includes forming a support structure at the edge of a thinned wafer that is encapsulated by a protection layer. The support structure can be an adhesive layer enclosing the protection layer, a dielectric-filled trench embedded in the thinned wafer and surrounding the protection layer, or a housing affixing the edge of the thinned wafer.

摘要翻译： 处理薄晶片的方法包括在由保护层封装的薄化晶片的边缘处形成支撑结构。 支撑结构可以是包围保护层的粘合剂层，嵌入在薄化晶片中并围绕保护层的介电填充沟槽或者固定薄化晶片的边缘的壳体。

公开(公告)号：US08691664B2

公开(公告)日：2014-04-08

申请号：US12685523

申请日：2010-01-11

申请人： Ku-Feng Yang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Jung-Chih Hu

发明人： Ku-Feng Yang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Jung-Chih Hu

IPC分类号： H01L21/00

CPC分类号： H01L21/30625 ,  H01L21/30608 ,  H01L21/3212 ,  H01L21/76898 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/13109 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/81193 ,  H01L2224/9202 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01079

摘要： A method of forming a semiconductor device is presented. A conductor is embedded within a substrate, wherein the substrate contains a non-conducting material. The backside of the substrate is ground to a thickness wherein at least 1 μm of the non-conducting material remains on the backside covering the conductor embedded within the substrate. Chemical mechanical polishing (CMP) is employed with an undiscerning slurry to the backside of the substrate, thereby planarizing the substrate and exposing the conductive material. A spin wet-etch, with a protective formulation, is employed to remove a thickness y of the non-conducting material from the backside of the substrate, thereby causing the conductive material to uniformly protrude from the backside of the substrate.

摘要翻译： 提出了一种形成半导体器件的方法。 导体嵌入衬底内，其中衬底含有非导电材料。 将衬底的背面研磨成厚度，其中至少1μm的非导电材料保留在覆盖衬底内的导体的背面上。 采用化学机械抛光（CMP），其具有不透明的浆料到衬底的背面，由此平坦化衬底并暴露导电材料。 使用具有保护性配方的旋转湿蚀刻从衬底的背面除去非导电材料的厚度y，从而使导电材料从衬底的背面均匀地突出。

公开(公告)号：US08232140B2

公开(公告)日：2012-07-31

申请号：US12731281

申请日：2010-03-25

申请人： Ku-Feng Yang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Tsung-Ding Wang

发明人： Ku-Feng Yang ,  Weng-Jin Wu ,  Wen-Chih Chiou ,  Tsung-Ding Wang

IPC分类号： H01L21/00

CPC分类号： H01L23/3114 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/16 ,  H01L24/32 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/80006 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2224/83005 ,  H01L2224/8385 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/83

摘要： A method for thin wafer handling and processing is provided. In one embodiment, the method comprises providing a wafer having a plurality of semiconductor chips, the wafer having a first side and a second side. A plurality of dies are attached to the first side of the wafer, at least one of the dies are bonded to at least one of the plurality of semiconductor chips. A wafer carrier is provided, wherein the wafer carrier is attached to the second side of the wafer. The first side of the wafer and the plurality of dies are encapsulated with a planar support layer. A first adhesion tape is attached to the planar support layer. The wafer carrier is then removed from the wafer and the wafer is diced into individual semiconductor packages.

摘要翻译： 提供了一种用于薄晶片处理和处理的方法。 在一个实施例中，该方法包括提供具有多个半导体芯片的晶片，该晶片具有第一侧和第二侧。 多个管芯附接到晶片的第一侧，至少一个管芯被结合到多个半导体芯片中的至少一个。 提供晶片载体，其中晶片载体附接到晶片的第二侧。 晶片的第一侧和多个管芯被平坦的支撑层封装。 第一粘合带附接到平面支撑层。 然后将晶片载体从晶片上移除，并将晶片切成单独的半导体封装。

公开(公告)号：US20090311829A1

公开(公告)日：2009-12-17

申请号：US12140695

申请日：2008-06-17

申请人： Ku-Feng Yang ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Ming-Chung Sung

发明人： Ku-Feng Yang ,  Wen-Chih Chiou ,  Weng-Jin Wu ,  Ming-Chung Sung

IPC分类号： H01L21/48 ,  H01L21/44

CPC分类号： H01L24/94 ,  H01L21/561 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/48

摘要： An integrated circuit structure includes a bottom semiconductor chip; a top die bonded onto the bottom semiconductor chip; a protecting material encircling the bottom die and on the bottom semiconductor chip; and a planar dielectric layer over the top die and the protecting material. The protecting material has a top surface leveled with a top surface of the top die.

摘要翻译： 集成电路结构包括底部半导体芯片; 顶部芯片结合到底部半导体芯片上; 围绕底模和底部半导体芯片的保护材料; 以及在顶模和保护材料上方的平面介电层。 保护材料具有与顶模的顶表面平齐的顶表面。

公开(公告)号：US08803316B2

公开(公告)日：2014-08-12

申请号：US13311692

申请日：2011-12-06

申请人： Yung-Chi Lin ,  Hsin-Yu Chen ,  Wen-Chih Chiou ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Jing-Cheng Lin

发明人： Yung-Chi Lin ,  Hsin-Yu Chen ,  Wen-Chih Chiou ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Jing-Cheng Lin

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/11011 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1405 ,  H01L2224/14104 ,  H01L2224/73204 ,  H01L2924/01028 ,  H01L2924/0132 ,  H01L2924/067 ,  H01L2924/0705 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

摘要： A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.

摘要翻译： 一种器件包括具有正面和背面的衬底，从衬底的背面延伸到前侧的通孔，以及位于衬底的背面和通孔上方的导电焊盘。 导电垫具有基本平坦的顶表面。 导电凸块在基本上平坦的顶表面上方具有非平面的顶表面，并且与通孔对准。 导电凸块和导电垫由相同的材料形成。 在导电凸块和导电垫之间不形成界面。

公开(公告)号：US20130140690A1

公开(公告)日：2013-06-06

申请号：US13311692

申请日：2011-12-06

申请人： Yung-Chi Lin ,  Hsin-Yu Chen ,  Wen-Chih Chiou ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Jing-Cheng Lin

发明人： Yung-Chi Lin ,  Hsin-Yu Chen ,  Wen-Chih Chiou ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Jing-Cheng Lin

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L23/49827 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/11011 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1405 ,  H01L2224/14104 ,  H01L2224/73204 ,  H01L2924/01028 ,  H01L2924/0132 ,  H01L2924/067 ,  H01L2924/0705 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

摘要： A device includes a substrate having a front side and a backside, a through-via extending from the backside to the front side of the substrate, and a conductive pad on the backside of the substrate and over the through-via. The conductive pad has a substantially planar top surface. A conductive bump has a non-planar top surface over the substantially planar top surface and aligned to the through-via. The conductive bump and the conductive pad are formed of a same material. No interface is formed between the conductive bump and the conductive pad.

公开(公告)号：US09059262B2

公开(公告)日：2015-06-16

申请号：US13033733

申请日：2011-02-24

申请人： Yuan-Hung Liu ,  Ku-Feng Yang ,  Pei-Ching Kuo ,  Ming-Tsu Chung ,  Hsin-Yu Chen ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

发明人： Yuan-Hung Liu ,  Ku-Feng Yang ,  Pei-Ching Kuo ,  Ming-Tsu Chung ,  Hsin-Yu Chen ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC分类号： H01L23/52 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76879 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2225/06541 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： An integrated circuit includes a substrate having a first surface and a second surface. At least one conductive structure continuously extends through the substrate. At least one sidewall of the at least one conductive structure is spaced from a sidewall of the substrate by an air gap.

摘要翻译： 集成电路包括具有第一表面和第二表面的基板。 至少一个导电结构连续地延伸穿过衬底。 所述至少一个导电结构的至少一个侧壁通过气隙与衬底的侧壁间隔开。

公开(公告)号：US09006101B2

公开(公告)日：2015-04-14

申请号：US13601265

申请日：2012-08-31

申请人： Hsin-Yu Chen ,  Ku-Feng Yang ,  Tasi-Jung Wu ,  Lin-Chih Huang ,  Yuan-Hung Liu ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

发明人： Hsin-Yu Chen ,  Ku-Feng Yang ,  Tasi-Jung Wu ,  Lin-Chih Huang ,  Yuan-Hung Liu ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L23/31

CPC分类号： H01L23/528 ,  H01L21/76807 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5384 ,  H01L27/0617 ,  H01L2221/1031 ,  H01L2224/13 ,  H01L2924/13091 ,  H01L2924/00

摘要： An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a first metal line and a dielectric layer formed over the first metallization layer, wherein the dielectric layer comprises a metal structure having a bottom surface coplanar with a top surface of the first metal line.

摘要翻译： 一种装置包括形成在衬底的第一侧上的层间绝缘层，形成在层间介电层上的第一金属化层，其中第一金属化层包括形成在第一金属化层上的第一金属线和介电层，其中， 电介质层包括具有与第一金属线的顶表面共面的底表面的金属结构。

公开(公告)号：US08803322B2

公开(公告)日：2014-08-12

申请号：US13272506

申请日：2011-10-13

申请人： Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Yi-Hsiu Chen ,  Ebin Liao ,  Yuan-Hung Liu ,  Wen-Chih Chiou

发明人： Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Yi-Hsiu Chen ,  Ebin Liao ,  Yuan-Hung Liu ,  Wen-Chih Chiou

IPC分类号： H01L23/48

CPC分类号： H01L23/5226 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L2224/05006 ,  H01L2224/05009 ,  H01L2224/05546 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： The embodiments of forming a through substrate via (TSV) structure described enable reducing risk of damaging gate structures due to over polishing of an inter-level dielectric layer (ILD) layer. The TSV structure with a wider opening near one end also enables better gapfill.

摘要翻译： 形成通过（TSV）通孔的结构的实施例能够降低由于层间电介质层（ILD）层的过度抛光而损坏栅极结构的风险。 在一端附近具有较宽开口的TSV结构还可实现更好的间隙填充。

公开(公告)号：US20120083116A1

公开(公告)日：2012-04-05

申请号：US12895296

申请日：2010-09-30

申请人： Ku-Feng Yang ,  Yung-Chi Lin ,  Hung-Pin Chang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

发明人： Ku-Feng Yang ,  Yung-Chi Lin ,  Hung-Pin Chang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC分类号： H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13025 ,  H01L2924/00013 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： A device includes a substrate having a first surface, and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the substrate. A dielectric layer is disposed over the substrate. A metal pad is disposed in the dielectric layer and physically contacting the TSV, wherein the metal pad and the TSV are formed of a same material, and wherein no layer formed of a material different from the same material is between and spacing the TSV and the metal pad apart from each other.

摘要翻译： 一种器件包括具有第一表面的衬底和与第一表面相对的第二表面。 贯穿基板通孔（TSV）从基板的第一表面延伸到第二表面。 电介质层设置在衬底上。 金属焊盘设置在电介质层中并物理接触TSV，其中金属焊盘和TSV由相同的材料形成，并且其中由不同于相同材料的材料形成的层不在其间并且使TSV和 金属垫彼此分开。