公开(公告)号：US20170280562A1

公开(公告)日：2017-09-28

申请号：US15079811

申请日：2016-03-24

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  David Francis Berdy ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H05K1/18 ,  H05K3/10 ,  H05K3/40 ,  H03H7/01 ,  H05K3/30

CPC classification number: H05K1/181 ,  H01L21/56 ,  H01L23/12 ,  H01L23/15 ,  H01L23/28 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H03H7/0138 ,  H05K1/0218 ,  H05K1/141 ,  H05K3/10 ,  H05K3/303 ,  H05K3/4007 ,  H05K2201/042 ,  H05K2201/045 ,  H05K2201/09227 ,  H05K2201/1003 ,  H05K2201/10098 ,  H05K2201/10962 ,  H05K2201/2036

Abstract: Passive device assembly for accurate ground plane control is disclosed. A passive device assembly includes a device substrate conductively coupled to a ground plane separation control substrate. A passive device disposed on a lower surface of the device substrate is separated from an embedded ground plane mounted on a lower surface of the ground plane separation control substrate by a separation distance. The separation distance is accurately controlled to minimize undesirable interference that may occur to the passive device. The separation distance is provided inside the passive device assembly. Conductive mounting pads are disposed on the lower surface of the ground plane separation control substrate to support accurate alignment of the passive device assembly on a circuit board. By providing sufficient separation distance inside the passive device assembly, the passive device assembly can be precisely mounted onto any circuit board regardless of specific design and layout of the circuit board.

公开(公告)号：US20170271266A1

公开(公告)日：2017-09-21

申请号：US15074750

申请日：2016-03-18

Applicant: QUALCOMM Incorporated

Inventor： Daeik Kim ,  Jie Fu ,  Changhan Yun ,  Chin-Kwan Kim ,  Manuel Aldrete ,  Chengjie Zuo ,  Mario Velez ,  Jonghae Kim

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.

公开(公告)号：US09449753B2

公开(公告)日：2016-09-20

申请号：US14155244

申请日：2014-01-14

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Xiangdong Zhang ,  Jonghae Kim ,  Je-Hsiung Lan

IPC: H01F5/00 ,  H01F27/29 ,  H01F27/30 ,  H01F27/28 ,  H01F41/04 ,  H01F17/00

CPC classification number: H01F41/041 ,  H01F17/0013 ,  H01F27/2804 ,  H01F41/042 ,  H01F2017/0053 ,  H01F2017/0073 ,  H01F2027/2809

Abstract: A particular device includes a substrate and a spiral inductor coupled to the substrate. The spiral inductor includes a first conductive spiral and a second conductive spiral overlaying the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate that is greater than the first thickness. A portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral.

Abstract translation: 特定器件包括衬底和耦合到衬底的螺旋电感器。 螺旋电感器包括覆盖第一导电螺旋的第一导电螺旋和第二导电螺旋。 螺旋电感器的最内圈的第一部分在垂直于衬底的方向上具有第一厚度。 最内圈的第一部分包括第一导电螺旋的第一部分，并且不包括第二导电螺旋。 最内圈的第二部分包括第二导电螺旋的第一部分。 螺旋电感器的最外圈的一部分在垂直于衬底的方向上具有大于第一厚度的第二厚度。 最外圈的一部分包括第一导电螺旋的第二部分和第二导电螺旋的第二部分。

公开(公告)号：US09343403B2

公开(公告)日：2016-05-17

申请号：US14483944

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Jeffrey Lan ,  David Francis Berdy ,  Chengjie Zuo ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Niranjan Sunil Mudakatte ,  Robert Paul Mikulka ,  Jonghae Kim

IPC: H01L23/522 ,  H01L21/283 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L21/283 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5329 ,  H01L27/01 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a substrate. The integrated circuit device also includes a first conductive stack including a back-end-of-line (BEOL) conductive layer at a first elevation with reference to the substrate. The integrated circuit device also includes a second conductive stack including the BEOL conductive layer at a second elevation with reference to the substrate. The second elevation differs from the first elevation.

Abstract translation: 集成电路器件包括衬底。 集成电路器件还包括第一导电叠层，其包括参考衬底的第一高度处的后端行（BEOL）导电层。 集成电路器件还包括第二导电叠层，其包括相对于衬底的第二高度处的BEOL导电层。 第二个高程与第一个高程不同。

公开(公告)号：US09275786B2

公开(公告)日：2016-03-01

申请号：US14335609

申请日：2014-07-18

Applicant: QUALCOMM Incorporated

Inventor： David Francis Berdy ,  Chengjie Zuo ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Jonghae Kim

IPC: H01F5/00 ,  H01F27/28 ,  H01F27/29 ,  H01F41/04

CPC classification number: H01F41/041 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/29 ,  H01F2017/004 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.

Abstract translation: 三维（3D）正交电感器对被嵌入并由衬底支撑，并且具有第一电感器，其具有卷绕第一绕组轴线的第一线圈和具有卷绕第二绕组轴线的第二线圈的第二电感器 。 第二卷绕轴线与第一卷绕轴线正交。 第二绕组轴线在第一绕组轴线处于衬底内的交点处。

公开(公告)号：US20150334847A1

公开(公告)日：2015-11-19

申请号：US14811813

申请日：2015-07-28

Applicant: QUALCOMM Incorporated

Inventor： Changhan Yun ,  Francesco Carobolante ,  Chengjie Zuo ,  Jonghae Kim ,  Mario Francisco Velez ,  Lawrence D. Smith ,  Matthew M. Nowak

IPC: H05K3/10 ,  H05K3/00 ,  H05K3/30

CPC classification number: H05K1/165 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0262 ,  H05K3/0091 ,  H05K3/10 ,  H05K3/30 ,  H05K7/1092 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49147 ,  Y10T29/49156

Abstract: A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.

Abstract translation: 两级供电网络包括电压调节器和插入器。 插入器包括具有嵌入式电感器的封装衬底。 嵌入式电感器包括一组迹线和一组在迹线的相对端处的通过衬底通孔。 插入器耦合到电压调节器。 两级供电网络还包括由封装基板支撑的半导体管芯。 两级供电网络还包括由包装基板支撑的电容器。 电容器可操作以提供与半导体管芯相关联的去耦电容和电容，以降低电压调节器的开关噪声。

公开(公告)号：US20150303148A1

公开(公告)日：2015-10-22

申请号：US14254764

申请日：2014-04-16

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Mario Francisco Velez ,  Jonghae Kim ,  Matthew Michael Nowak ,  Chengjie Zuo ,  Changhan Hobie Yun ,  David Francis Berdy ,  Robert Paul Mikulka

IPC: H01L23/552 ,  H01L23/00 ,  H05K9/00 ,  H01L23/04 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/32 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01R12/7076 ,  H01R12/714 ,  H05K1/181 ,  H05K9/0032 ,  H05K2201/10189 ,  H05K2201/1053 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Some novel features pertain to an integrated device package (e.g., die package) that includes a package substrate, a die, an encapsulation layer and a first set of metal layers. The package substrate includes a first surface and a second surface. The die is coupled to the first surface of the package substrate. The encapsulation layer encapsulates the die. The first set of metal layers is coupled to a first exterior surface of the encapsulation layer. In some implementations, the first set of metal layers is configured to operate as a die-to-wire connector of the integrated device package. In some implementations, the integrated device package includes a second set of metal layers coupled to the second surface of the package substrate. In some implementations, the integrated device package includes a second set of metal layers coupled to a second exterior surface of the encapsulation layer.

Abstract translation: 一些新颖特征涉及包括封装衬底，管芯，封装层和第一组金属层的集成器件封装（例如管芯封装）。 封装衬底包括第一表面和第二表面。 管芯耦合到封装衬底的第一表面。 封装层封装模具。 第一组金属层耦合到封装层的第一外表面。 在一些实施方案中，第一组金属层被配置为作为集成器件封装的管芯到线连接器工作。 在一些实施方案中，集成器件封装包括耦合到封装衬底的第二表面的第二组金属层。 在一些实施方案中，集成器件封装包括耦合到封装层的第二外表面的第二组金属层。

公开(公告)号：US09101068B2

公开(公告)日：2015-08-04

申请号：US13830033

申请日：2013-03-14

Applicant: QUALCOMM Incorporated

Inventor： Changhan Yun ,  Francesco Carobolante ,  Chengjie Zuo ,  Jonghae Kim ,  Mario Francisco Velez ,  Lawrence D. Smith ,  Matthew M. Nowak

IPC: H05K7/00 ,  H05K7/10 ,  H05K1/02 ,  H05K1/16 ,  H01L23/498

CPC classification number: H05K1/165 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0262 ,  H05K3/0091 ,  H05K3/10 ,  H05K3/30 ,  H05K7/1092 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49147 ,  Y10T29/49156

Abstract: A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.

Abstract translation: 两级供电网络包括电压调节器和插入器。 插入器包括具有嵌入式电感器的封装衬底。 嵌入式电感器包括一组迹线和一组在迹线的相对端处的通过衬底通孔。 插入器耦合到电压调节器。 两级供电网络还包括由封装基板支撑的半导体管芯。 两级供电网络还包括由包装基板支撑的电容器。 电容器可操作以提供与半导体管芯相关联的去耦电容和电容，以降低电压调节器的开关噪声。

公开(公告)号：US20150115405A1

公开(公告)日：2015-04-30

申请号：US14069201

申请日：2013-10-31

Applicant: QUALCOMM Incorporated

Inventor： Xiaoxia Wu ,  Yunqiang Yang ,  Chengjie Zuo ,  Durodami Joscelyn Lisk

IPC: H01L23/522 ,  H01L21/48 ,  H01L49/02

CPC classification number: H01L21/486 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/645 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L28/10 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/30107 ,  H01L2924/014 ,  H01L2924/00

Abstract: Some implementations provide an interposer that includes a substrate, a first passive device in the substrate, and a second passive device. The first passive device includes a first set of through substrate vias (TSVs) in the substrate. The second passive device is configured to wirelessly couple to the first passive device. In some implementations, the second passive device includes a second set of through substrate vias (TSVs) in the substrate. In some implementations, the second passive device is configured to inductively couple to the first passive device. In some implementations, the first passive device is a first inductor and the second passive device is a second inductor. In some implementations, the interposer further includes a first set of interconnects coupled to the first set of TSVs, and a second set of interconnects coupled to the second set of TSVs.

Abstract translation: 一些实施方案提供了一种插入器，其包括衬底，衬底中的第一无源器件和第二无源器件。 第一无源器件包括衬底中的第一组贯通衬底通孔（TSV）。 第二无源设备被配置为无线地耦合到第一无源设备。 在一些实施方案中，第二无源器件包括衬底中的第二组穿通衬底通孔（TSV）。 在一些实现中，第二无源设备被配置为感应地耦合到第一无源设备。 在一些实施方案中，第一无源器件是第一电感器，第二无源器件是第二电感器。 在一些实现中，插入器还包括耦合到第一组TSV的第一组互连以及耦合到第二组TSV的第二组互连。

公开(公告)号：US20150048480A1

公开(公告)日：2015-02-19

申请号：US13968627

申请日：2013-08-16

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Young Kyu Song ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L23/498 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L23/49827 ,  H01L21/76885 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/642 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2224/16225 ,  H01L2225/06572 ,  H01L2924/19105

Abstract: Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.

Abstract translation: 一些新颖的特征涉及一种半导体器件，其包括衬底，穿过衬底的第一腔体。 第一腔被配置为被互连材料（例如，焊球）占据。 衬底还包括耦合到第一腔的第一侧壁的第一金属层。 衬底还包括在衬底的第一表面上的第一集成无源器件（IPD），第一IPD耦合到第一金属层。 在一些实施方案中，基底是玻璃基底。 在一些实现中，第一IPD是至少一个电容器，电感器和/或电阻器中的一个。 在一些实施方式中，半导体器件还包括在衬底的第二表面上的第二集成无源器件（IPD）。 第二IPD耦合到第一金属层。