公开(公告)号：US11600766B2

公开(公告)日：2023-03-07

申请号：US16064420

申请日：2016-12-21

Applicant: Soitec

Inventor： Bruno Ghyselen ,  Ionut Radu ,  Jean-Marc Bethoux

IPC: H01L41/312 ,  H01L41/319 ,  H03H3/02 ,  H01L41/187 ,  C30B25/18 ,  C30B29/22 ,  H01L41/08 ,  H01L41/09 ,  H01L41/335 ,  H03H3/08 ,  H03H9/25 ,  H03H9/54 ,  H03H9/64 ,  H01L41/316 ,  C30B29/30

Abstract: A method for manufacturing a monocrystalline piezoelectric material layer includes providing a donor substrate made of the piezoelectric material, providing a receiving substrate, transferring a so-called “seed layer” of the donor substrate onto the receiving substrate, and using epitaxy of the piezoelectric material on the seed layer until the desired thickness for the monocrystalline piezoelectric layer is obtained.

公开(公告)号：US20210058058A1

公开(公告)日：2021-02-25

申请号：US17075465

申请日：2020-10-20

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H01L41/312 ,  H01L41/08 ,  H01L41/313 ,  H03H3/10

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

公开(公告)号：US20200228088A1

公开(公告)日：2020-07-16

申请号：US16829604

申请日：2020-03-25

Applicant: Soitec

Inventor： Marcel Broekaart ,  Thierry Barge ,  Pascal Guenard ,  Ionut Radu ,  Eric Desbonnets ,  Oleg Kononchuk

IPC: H03H9/02 ,  H01L41/312 ,  H03H3/02 ,  H01L27/20 ,  H01L41/047 ,  H03H3/04 ,  H03H3/10 ,  H03H9/13 ,  H03H9/145 ,  H03H9/17 ,  H03H9/25 ,  H03H9/56 ,  H03H9/64

Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.

公开(公告)号：US20180316329A1

公开(公告)日：2018-11-01

申请号：US15769698

申请日：2016-10-17

Applicant: Soitec

Inventor： Pascal Guenard ,  Ionut Radu ,  Didier Landru ,  Eric Desbonnets

IPC: H03H3/04 ,  H01L41/053 ,  H01L41/312 ,  H03H9/02 ,  H03H9/05

CPC classification number: H01L41/312 ,  H01L41/0805 ,  H03H9/02102 ,  H03H9/02574

Abstract: A composite structure for an acoustic wave device comprising a heterostructure includes: a useful layer of piezoelectric material, having a first face and a second face, the first face being arranged at a first bonding interface on a support substrate having a coefficient of thermal expansion less than that of the useful layer, wherein the composite structure further comprises a functional layer, an entire surface of which is arranged at a second bonding interface on the second face of the useful layer and having a coefficient of thermal expansion less than that of the useful layer. Methods are used for producing such a composite structure.

公开(公告)号：US09905531B2

公开(公告)日：2018-02-27

申请号：US14411741

申请日：2013-06-05

Applicant: Soitec

Inventor： Ionut Radu ,  Marcel Broekaart ,  Arnaud Castex ,  Gweltaz Gaudin ,  Gregory Riou

IPC: H01L23/00 ,  H01L21/18 ,  H01L21/306 ,  H01L21/66

CPC classification number: H01L24/83 ,  H01L21/187 ,  H01L21/30604 ,  H01L21/30625 ,  H01L22/12 ,  H01L23/562 ,  H01L24/32 ,  H01L2224/29124 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29176 ,  H01L2224/2918 ,  H01L2224/29181 ,  H01L2224/29184 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83895 ,  H01L2924/01014 ,  H01L2924/0504 ,  H01L2924/10253 ,  H01L2924/201 ,  Y10T428/12493 ,  Y10T428/12639 ,  Y10T428/12646 ,  Y10T428/12653 ,  Y10T428/12674

Abstract: Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa. The method further comprises, after the step of initiating the propagation of a bonding wave, a step of determining the level of stress induced during bonding of the two wafers, the level of stress being determined on the basis of a stress parameter Ct calculated using the formula Ct=Rc/Ep, where: Rc corresponds to the radius of curvature (in km) of the two-wafer assembly and Ep corresponds to the thickness (in μm) of the two-wafer assembly. The method further comprises a step of validating the bonding when the level of stress Ct determined is greater than or equal to 0.07.

公开(公告)号：US20150364364A1

公开(公告)日：2015-12-17

申请号：US14377738

申请日：2013-01-28

Applicant: SOITEC

Inventor： Gweltaz Gaudin ,  Oleg Kononchuk ,  Ionut Radu

IPC: H01L21/762 ,  B32B7/04 ,  B32B9/04

CPC classification number: H01L21/76254 ,  B32B7/04 ,  B32B9/04 ,  B32B2457/14 ,  Y10T428/24802

Abstract: A method comprising the following steps: providing a support substrate and a donor substrate, forming an embrittlement region in the donor substrate so as to delimit a first portion and a second portion on either side of the embrittlement region, assembling the donor substrate on the support substrate, fracturing the donor substrate along the embrittlement. In addition, the method comprises a step consisting of forming a compressive stress layer in the donor substrate so as to delimit a so-called confinement region interposed between the compressive stress layer and the embrittlement region.

Abstract translation: 一种包括以下步骤的方法：提供支撑衬底和供体衬底，在所述供体衬底中形成脆化区域，以限定所述脆化区域的任一侧上的第一部分和第二部分，将所述施主衬底组装在所述支撑体上 底物，沿着脆化破坏施主衬底。 此外，该方法包括在施主衬底中形成压应力层以限定介于压应力层和脆化区之间的所谓约束区的步骤。

公开(公告)号：US20130299997A1

公开(公告)日：2013-11-14

申请号：US13937779

申请日：2013-07-09

Applicant: Soitec

Inventor： Mariam Sadaka ,  Ionut Radu

IPC: H01L23/538

CPC classification number: H01L23/5384 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2221/6839 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/03616 ,  H01L2224/0362 ,  H01L2224/0381 ,  H01L2224/05009 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08146 ,  H01L2224/80006 ,  H01L2224/80065 ,  H01L2224/802 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/80 ,  H01L2924/00

Abstract: Methods of forming bonded semiconductor structures include temporarily, directly bonding together semiconductor structures, thinning at least one of the semiconductor structures, and subsequently permanently bonding the thinned semiconductor structure to another semiconductor structure. The temporary, direct bond may be established without the use of an adhesive. Bonded semiconductor structures are fabricated in accordance with such methods.

Abstract translation: 形成键合的半导体结构的方法包括暂时将半导体结构直接结合在一起，使半导体结构中的至少一个变薄，然后将稀化的半导体结构永久地结合到另一个半导体结构。 可以在不使用粘合剂的情况下建立临时的直接粘合。 结合的半导体结构根据这样的方法制造。

公开(公告)号：US20130256907A1

公开(公告)日：2013-10-03

申请号：US13900157

申请日：2013-05-22

Applicant: Soitec

Inventor： Mariam Sadaka ,  Ionut Radu

IPC: H01L23/00 ,  H01L23/538

CPC classification number: H01L21/76254 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/98 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/03616 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08121 ,  H01L2224/08146 ,  H01L2224/0903 ,  H01L2224/16145 ,  H01L2224/27444 ,  H01L2224/27616 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80 ,  H01L2224/80006 ,  H01L2224/80011 ,  H01L2224/80121 ,  H01L2224/802 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80805 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80905 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83011 ,  H01L2224/83022 ,  H01L2224/83121 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/832 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83805 ,  H01L2224/83896 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/3512

Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

公开(公告)号：US20250006492A1

公开(公告)日：2025-01-02

申请号：US18697809

申请日：2022-09-21

Applicant: Soitec

Inventor： Hugo Biard ,  Ionut Radu ,  Frédéric Allibert

IPC: H01L21/02

Abstract: A method of fabricating a composite structure including a thin layer of single-crystal silicon carbide on a polycrystalline silicon carbide carrier substrate includes providing an initial substrate of single-crystal silicon carbide and a carrier substrate of polycrystalline silicon carbide. A porous layer is formed on the initial substrate, and a superficial layer of amorphous silicon carbide is formed on the carrier substrate and/or on the porous layer. The initial substrate and the carrier substrate are joined to form a first intermediate structure, which is heat treated at an elevated temperature to crystallize the superficial layer, at least partly in the form of single-crystal silicon carbide, to form the thin layer and to form a second intermediate structure, which is separated in the porous layer to form the composite structure and a remainder of the initial substrate.

公开(公告)号：US12101080B2

公开(公告)日：2024-09-24

申请号：US18302440

申请日：2023-04-18

Applicant: Soitec

Inventor： Arnaud Castex ,  Daniel Delprat ,  Bernard Aspar ,  Ionut Radu

IPC: H03H9/02 ,  H03H3/04 ,  H03H3/10 ,  H03H9/64 ,  H10N30/00 ,  H10N30/072 ,  H10N30/073 ,  H10N30/082 ,  H10N30/086 ,  H10N30/853 ,  H10N35/01

CPC classification number: H03H9/02834 ,  H03H3/04 ,  H03H3/10 ,  H03H9/02574 ,  H10N30/072 ,  H10N30/073 ,  H10N30/704 ,  H10N30/8542 ,  H03H9/6496 ,  H10N30/082 ,  H10N30/086 ,  H10N35/01 ,  Y10T29/42

Abstract: The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.