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    Package structure
    32.
    发明授权
    Package structure 有权

    公开(公告)号：US11282825B2

    公开(公告)日：2022-03-22

    申请号：US16877504

    申请日：2020-05-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Shu Lin ,  Tsung-Yu Chen ,  Wensen Hung

    IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/40 ,  H01L23/46

    Abstract: A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.

    PACKAGE STRUCTURE
    33.
    发明申请
    PACKAGE STRUCTURE 有权

    公开(公告)号：US20210366889A1

    公开(公告)日：2021-11-25

    申请号：US16877504

    申请日：2020-05-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Shu Lin ,  Tsung-Yu Chen ,  Wensen Hung

    IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/46 ,  H01L23/40

    Abstract: A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.

    Heat Spreading Device and Method
    34.
    发明申请
    Heat Spreading Device and Method 有权

    公开(公告)号：US20210280491A1

    公开(公告)日：2021-09-09

    申请号：US17328266

    申请日：2021-05-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Shu Lin ,  Wensen Hung ,  Hung-Chi Li ,  Tsung-Yu Chen

    IPC: H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

    Abstract: In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.

    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    36.
    发明申请
    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200381382A1

    公开(公告)日：2020-12-03

    申请号：US16997941

    申请日：2020-08-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Yen Chiu ,  Shou-Yi Wang ,  Tsung-Shu Lin

    IPC: H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/31

    Abstract: A semiconductor package includes a semiconductor die and a connection structure. The semiconductor die is laterally encapsulated by an insulating encapsulant. The connection structure is disposed on the semiconductor die, the connection structure is electrically connected to the semiconductor die, and the connection structure includes at least one first via, first pad structures, second vias, a second pad structure and a conductive terminal. The at least one first via is disposed over and electrically connected to the semiconductor die. The first pad structures are disposed over the at least one first via, wherein the at least one first via contacts at least one of the first pad structures. The second vias are disposed over the first pad structures, wherein the second vias contact the first pad structures. The second pad structure is disposed over and contacts the second vias, wherein a vertical projection of each of first pad structures overlaps with a vertical projection of the second pad structure, and an overall area of the vertical projections of the first pad structures is smaller than an area of the vertical projection of the second pad structure. The conductive terminal is disposed over and connects with the second pad structure.

    Semiconductor Device and Methods of Manufacture
    39.
    发明申请
    Semiconductor Device and Methods of Manufacture 有权

    公开(公告)号：US20250022763A1

    公开(公告)日：2025-01-16

    申请号：US18352363

    申请日：2023-07-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Han Tsai ,  Tsung-Yu Chen ,  Hong-Yu Guo ,  Tsung-Shu Lin

    IPC: H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/29 ,  H01L25/10

    Abstract: Semiconductor device and methods of manufacture are provided. In an embodiment, the a semiconductor device may include a first semiconductor die; an oxide layer on the first semiconductor die, wherein the first semiconductor die has a first top surface opposite the oxide layer; a first insulating material encapsulating the first semiconductor die and the oxide layer, wherein the first insulating material has a second top surface planar with the first top surface; and a first polymer buffer disposed between a sidewall of the first semiconductor die and a sidewall of the oxide layer, wherein the first polymer buffer has a third top surface planar with both the first top surface and the second top surface.

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