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    MANAGING WAIT STATES FOR MEMORY ACCESS
    32.
    发明申请
    MANAGING WAIT STATES FOR MEMORY ACCESS 有权
    管理用于存储器访问的等待状态

    公开(公告)号：US20160335000A1

    公开(公告)日：2016-11-17

    申请号：US15223227

    申请日：2016-07-29

    申请人： Atmel Corporation

    发明人： Frode Milch Pedersen ,  Sebastien Jouin ,  Ian Fullerton

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0611 ,  G06F3/0655 ,  G06F3/0679 ,  G06F13/1689 ,  G06F13/4217 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

    摘要： A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.

    摘要翻译： 从非易失性存储器件接收指示非易失性存储器件的当前访问时间的锁存信号。 访问时间表示非易失性存储器件根据数据请求使数据可用的时间量。 接收总线系统时钟信号。 评估锁存信号，并且基于评估来调整非易失性存储器件的等待状态。 等待状态表示由中央处理单元用于访问非易失性存储器件的总线系统时钟的周期数。 产生基于调整后的等待状态触发的总线系统数据就绪信号。 当触发时，总线系统数据就绪信号表示响应于该请求可用数据。

    HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE
    33.
    发明申请
    HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE 审中-公开
    具有改进的指令地址和芯片选择信号模式的高容量存储器系统

    公开(公告)号：US20160314085A1

    公开(公告)日：2016-10-27

    申请号：US15101870

    申请日：2014-12-18

    申请人： RAMBUS INC.

    发明人： Frederick A. WARE ,  Abhijit ABHYANKAR ,  Suresh RAJAN

    IPC分类号： G06F13/16 ,  G06F13/42

    CPC分类号： G06F13/1673 ,  G06F13/4243

    摘要： A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

    摘要翻译： 存储器控制器和存储器模块中的缓冲器各自以两种模式运行，这取决于控制器和模块通过其连接的主板的类型。 在第一模式中，控制器独立地向每个模块发送解码的芯片选择信号，并且主板数据信道使用到每个模块的多点连接。 在第二模式中，母板具有到每个存储器模块的点对点数据信道和命令地址连接，并且控制器向每个模块发送完全编码的芯片选择信号组。 缓冲器以模态方式进行操作，以根据模式正确选择每个事务的一个或多个模块上的存储器设备的等级或部分等级。

    Programmable latency count to achieve higher memory bandwidth
    34.
    发明授权
    Programmable latency count to achieve higher memory bandwidth 有权
    可编程延迟计数，以实现更高的内存带宽

    公开(公告)号：US09477619B2

    公开(公告)日：2016-10-25

    申请号：US13913909

    申请日：2013-06-10

    申请人： Cypress Semiconductor Corporation

    发明人： Qamrul Hasan ,  Dawn M. Hopper ,  Clifford Alan Zitlaw

    IPC分类号： G06F13/40 ,  G06F13/16 ,  G06F13/42 ,  G06F3/06

    CPC分类号： G06F13/1689 ,  G06F3/0613 ,  G06F3/0655 ,  G06F3/0683 ,  G06F13/161 ,  G06F13/4243 ,  G06F13/4291

    摘要： Disclosed herein are system, method and/or computer program product embodiments for increasing memory bandwidth when accessing a plurality of memory devices. An embodiment operates by executing, by at least one processor, a first read operation to read data from a first memory device following an access time for the first memory device. The embodiment further includes executing, by the at least one processor, a second read operation to read data from a second memory device following an access time for the second memory device. The access time for the second memory device is substantially the same or longer than the access time for the first memory device plus a time it takes to read data from the first memory device.

    摘要翻译： 这里公开了用于在访问多个存储器设备时增加存储器带宽的系统，方法和/或计算机程序产品实施例。 实施例通过至少一个处理器执行第一读取操作，以在第一存储器设备的访问时间之后从第一存储器设备读取数据。 该实施例还包括由至少一个处理器执行第二读取操作，以在第二存储器设备的访问时间之后从第二存储器设备读取数据。 第二存储设备的访问时间与第一存储设备的访问时间基本相同或更长，加上从第一存储设备读取数据所花费的时间。

    IMPEDANCE COMPENSATION BASED ON DETECTING SENSOR DATA
    35.
    发明申请
    IMPEDANCE COMPENSATION BASED ON DETECTING SENSOR DATA 有权
    基于检测传感器数据的阻抗补偿

    公开(公告)号：US20160284386A1

    公开(公告)日：2016-09-29

    申请号：US14670411

    申请日：2015-03-27

    申请人： Intel Corporation

    发明人： James A. McCall ,  Kuljit S. Bains

    IPC分类号： G11C7/10 ,  G11C29/50 ,  G06F11/30 ,  G06F13/42

    CPC分类号： G06F11/3089 ,  G06F11/3037 ,  G06F11/3058 ,  G06F13/4243 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50008

    摘要： A memory subsystem manages memory I/O impedance compensation by the memory device monitoring a need for impedance compensation. Instead of a memory controller regularly sending a signal to have the memory device update the impedance compensation when a change is not needed, the memory device can indicate when it is ready to perform an impedance compensation change. The memory controller can send an impedance compensation signal to the memory device in response to a compensation flag set by the memory or in response to determining that a sensor value has changed in excess of a threshold.

    摘要翻译： 存储器子系统通过存储器件管理存储器I / O阻抗补偿，监测对阻抗补偿的需要。 代替存储器控制器定期发送信号以使得存储器件在不需要改变时更新阻抗补偿，存储器件可以指示何时准备好进行阻抗补偿改变。 存储器控制器可以响应于由存储器设置的补偿标志或响应于确定传感器值已经改变超过阈值而向阻塞补偿信号发送阻抗补偿信号。

    Calibration in a control device receiving from a source synchronous interface
    39.
    发明授权
    Calibration in a control device receiving from a source synchronous interface 有权
    从源同步接口接收的控制设备中进行校准

    公开(公告)号：US09355696B1

    公开(公告)日：2016-05-31

    申请号：US14534487

    申请日：2014-11-06

    申请人： Xilinx, Inc.

    发明人： Terence J. Magee ,  Xiaoqian Zhang

    IPC分类号： G11C7/10 ,  G11C7/22 ,  H03K5/14 ,  G11C11/00

    CPC分类号： G11C7/222 ,  G06F13/4243 ,  G11C11/005 ,  H03K5/14

    摘要： In an example, a control device includes a data path, a clock path, a multiplexing circuit, and a calibration unit. The data path comprises a data delay unit coupled to a data input of a sampling circuit. The clock path comprises a clock delay unit coupled to a clock input of the sampling circuit. The multiplexing circuit selectively couples a reference clock or a data bus to an input of the data delay unit, and selectively couples the reference clock or a source clock to an input of the clock delay unit. The calibration unit is coupled to a data output of the sampling circuit. The calibration unit is operable to adjust delay values of the data delay unit and the clock delay unit based on the data output of the sampling circuit to establish and maintain a relative delay between the data path and the clock path.

    摘要翻译： 在一个示例中，控制装置包括数据路径，时钟路径，复用电路和校准单元。 数据路径包括耦合到采样电路的数据输入的数据延迟单元。 时钟路径包括耦合到采样电路的时钟输入的时钟延迟单元。 多路复用电路将参考时钟或数据总线选择性地耦合到数据延迟单元的输入，并且将参考时钟或源时钟选择性地耦合到时钟延迟单元的输入。 校准单元耦合到采样电路的数据输出。 校准单元可操作以基于采样电路的数据输出来调整数据延迟单元和时钟延迟单元的延迟值，以建立和维持数据路径与时钟路径之间的相对延迟。