公开(公告)号：US07905014B2

公开(公告)日：2011-03-15

申请号：US11832378

申请日：2007-08-01

Applicant: Tomoyuki Ikeda

Inventor： Tomoyuki Ikeda

IPC: H01K3/10

CPC classification number: H01L23/50 ,  B32B3/10 ,  B32B7/02 ,  H01L23/49827 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/3011 ,  H05K1/115 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09827 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A multilayer core board 10 includes tapered first via hole conductors 51 extending from the outer surface of a first insulating layer 24 to conductive portions 42a of a power source layer 42, second via hole conductors 52 extending from the outer surface of a second insulating layer 26 to the conductive portions 42a of the power source layer 42, tapered third via hole conductors 53 extending from the outer surface of the second insulating layer 26 to conductive portions 40a of a ground layer 40, and fourth via hole conductors 54 extending from the outer surface of a center insulating layer 22 to the conductive portions 40a of the ground layer 40. The first via hole conductors 51 are tapered, and thus the interval distance to the adjacent first via hole conductor 51 is shorter than straight-shaped first via hole conductors, and thus the pitch of the first via hole conductor 51 at the positive pole side and the fourth via hole conductor 54 at the negative pole side can be sufficiently reduced. This point is applicable to the third via hole conductors 53.

Abstract translation: 多层芯板10包括从第一绝缘层24的外表面延伸到电源层42的导电部分42a的锥形第一通孔导体51，从第二绝缘层26的外表面延伸的第二通孔导体52 到电源层42的导电部分42a，从第二绝缘层26的外表面延伸到接地层40的导电部分40a的锥形第三通孔导体53，以及从外表面延伸的第四通孔导体54 第一通孔导体51是锥形的，因此与相邻的第一通路孔导体51的间隔距离比直形的第一通孔导体短， 因此正极侧的第一通孔导体51的间距和负极侧的第四通孔导体54的间距能够充分地再次 屈服 这点适用于第三通孔导体53。

公开(公告)号：US07886433B2

公开(公告)日：2011-02-15

申请号：US12007795

申请日：2008-01-15

Applicant: Won-Cheol Bae ,  Je-Gwang Yoo ,  Sang-Chul Lee ,  Doo-Hwan Lee

Inventor： Won-Cheol Bae ,  Je-Gwang Yoo ,  Sang-Chul Lee ,  Doo-Hwan Lee

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H05K1/185 ,  B32B3/06 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H05K2201/09509 ,  H05K2203/308 ,  Y10T29/49126 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T156/1056 ,  Y10T428/22 ,  H01L2224/82

Abstract: A component-embedded PCB and a method of manufacturing the PCB are disclosed. Using a method that includes perforating a cavity in a core substrate; inserting a component in the cavity; stacking a film layer over the core substrate; forming at least one post by selectively leaving behind the film layer in correspondence to a position of at least one electrode of the component; covering an insulation layer over the core substrate such that the post penetrates the insulation layer to be exposed at a surface of the insulation layer; and forming at least one via hole by removing the post, can provide increased precision and finer pitch. Also, since laser is not used when processing the vias, damage to the component that may occur due to the laser is prevented. Furthermore, tolerance defects may be decreased, as well as defects caused by residue left after processing.

Abstract translation: 公开了一种组件嵌入式PCB及其制造方法。 使用包括在芯基板中穿孔的方法; 将部件插入腔中; 在芯基板上堆叠薄膜层; 通过选择性地将所述膜层留在所述元件的至少一个电极的位置上而形成至少一个柱; 覆盖所述芯基板上的绝缘层，使得所述柱穿透所述绝缘层以在所述绝缘层的表面上暴露; 并且通过去除柱形成至少一个通孔，可以提供更高的精度和更细的间距。 此外，由于在加工通孔时不使用激光，因此防止了由于激光而可能发生的部件的损坏。 此外，可能会降低公差缺陷，以及加工后残留物造成的缺陷。

公开(公告)号：US07863724B2

公开(公告)日：2011-01-04

申请号：US12029574

申请日：2008-02-12

Applicant: Daniel Douriet ,  Francesco Preda ,  Brian L. Singletary ,  Lloyd A. Walls

Inventor： Daniel Douriet ,  Francesco Preda ,  Brian L. Singletary ,  Lloyd A. Walls

IPC: H01L23/52

CPC classification number: H01L21/768 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/0263 ,  H05K1/113 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/49165

Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

Abstract translation: 电路基板使用后馈电顶部电源连接来提供改进的布线灵活性和较低的电源电压降/功率损耗。 在基板的外边缘附近使用电镀通孔，以提供与作为电源平面的管芯相邻的基板的顶部金属层的电源连接。 引脚插入通过电镀通孔以进一步降低电源路径的电阻。 引脚的底端可以延伸越过基板的底部以提供用于电源连接的可焊接互连，或者引脚的底端可以被焊接到基板的底部金属层上的“点动”电路图案，其连接 引脚连接到包括基板的集成电路封装的一个或多个电源端子。

公开(公告)号：US07863706B2

公开(公告)日：2011-01-04

申请号：US11770690

申请日：2007-06-28

Applicant: Yaojian Lin

Inventor： Yaojian Lin

IPC: H01L29/00

CPC classification number: H01L27/016 ,  H01L21/77 ,  H05K1/162 ,  H05K1/167 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/09845

Abstract: A circuit system includes: forming a first electrode over a substrate; applying a dielectric layer over the first electrode and the substrate; forming a second electrode over the dielectric layer; and forming a dielectric structure from the dielectric layer with the dielectric structure within a first horizontal boundary of the first electrode.

Abstract translation: 电路系统包括：在衬底上形成第一电极; 在第一电极和衬底上施加电介质层; 在所述电介质层上形成第二电极; 以及在所述第一电极的第一水平边界内从具有所述电介质结构的介电层形成电介质结构。

公开(公告)号：US20100330797A1

公开(公告)日：2010-12-30

申请号：US12874397

申请日：2010-09-02

Applicant: Daniel Douriet ,  Francesco Preda ,  Brian L. Singletary ,  Lloyd A. Walls

Inventor： Daniel Douriet ,  Francesco Preda ,  Brian L. Singletary ,  Lloyd A. Walls

IPC: H01L21/768

CPC classification number: H01L21/768 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/0263 ,  H05K1/113 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/49165

Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

Abstract translation: 电路基板使用后馈电顶部电源连接来提供改进的布线灵活性和较低的电源电压降/功率损耗。 在基板的外边缘附近使用电镀通孔，以提供与作为电源平面的管芯相邻的基板的顶部金属层的电源连接。 引脚插入通过电镀通孔以进一步降低电源路径的电阻。 引脚的底端可以延伸越过基板的底部以提供用于电源连接的可焊接互连，或者引脚的底端可以被焊接到基板的底部金属层上的“点动”电路图案，其连接 引脚连接到包括基板的集成电路封装的一个或多个电源端子。

公开(公告)号：US20100307666A1

公开(公告)日：2010-12-09

申请号：US12479811

申请日：2009-06-07

Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

IPC: B32B37/00

CPC classification number: B32B37/02 ,  B32B38/06 ,  B32B2038/047 ,  B32B2457/08 ,  B32B2457/16 ,  H01G4/236 ,  H01G4/33 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2203/1461

Abstract: A method for fabricating a buried capacitor structure includes: laminating a first dielectric layer having a capacitor embedded therein with a second dielectric layer to bury the capacitor therebetween; forming a first circuit pattern on a first metal layer of the first dielectric layer and a second circuit pattern on a second metal layer of the second dielectric layer; depositing a first insulating layer and a second insulating layer on the first metal layer and the second metal layer, respectively; electrically connecting a positive electrode end and a negative electrode end of the capacitor to the second metal layer by a positive through-hole and a negative through-hole, thereby manufacturing the buried capacitor structure.

Abstract translation: 一种埋入式电容器结构的制造方法，其特征在于：将具有嵌入其中的电容器的第一电介质层与第二电介质层层叠， 在所述第一介电层的第一金属层上形成第一电路图案，在所述第二介电层的第二金属层上形成第二电路图案; 分别在第一金属层和第二金属层上沉积第一绝缘层和第二绝缘层; 通过正通孔和负通孔将电容器的正极端子和负极端子电连接到第二金属层，从而制造埋入式电容器结构。

公开(公告)号：US07847393B2

公开(公告)日：2010-12-07

申请号：US12257501

申请日：2008-10-24

Applicant: Naohiro Hirose ,  Hitoshi Ito ,  Yoshiyuki Iwata ,  Masanori Kawade ,  Hajime Yazu

Inventor： Naohiro Hirose ,  Hitoshi Ito ,  Yoshiyuki Iwata ,  Masanori Kawade ,  Hajime Yazu

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H01L23/49811 ,  H01L2224/05001 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/15312 ,  H05K1/111 ,  H05K1/112 ,  H05K3/28 ,  H05K3/321 ,  H05K3/3421 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/09381 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/0979 ,  H05K2201/10318 ,  Y10T428/239

Abstract: A package substrate 310 incorporating a substrate provided with a conductor layer 5, a conductive connecting pin 100 arranged to establish the electrical connection with a mother board and secured to the surface of the substrate, wherein a pad 16 for securing the conductive connecting pin is provided for the package substrate 310. The pad 16 is covered with an organic resin insulating layer 15 having an opening 18 through which the pad 16 is partially exposed to the outside. The conductive connecting pin 100 is secured to the pad exposed to the outside through the opening with a conductive adhesive agent 17 so that solution of the conductive connecting pin 100 from the substrate occurring, for example when mounting is performed is prevented.

Abstract translation: 一种包含衬底的封装衬底310，该衬底设置有导体层5，导电连接销100被布置成与母板建立电连接并固定到衬底的表面，其中提供用于固定导电连接销的衬垫16 用于封装衬底310.衬垫16被具有开口18的有机树脂绝缘层15覆盖，衬垫16通过该开口部分地暴露于外部。 导电连接销100通过导电粘合剂17通过开口固定到暴露于外部的焊盘，从而防止例如当执行安装时发生例如导电连接销100从基板的溶液。

公开(公告)号：US07832092B2

公开(公告)日：2010-11-16

申请号：US12041457

申请日：2008-03-03

Applicant: Takehiro Shirai ,  Masayuki Iwase

Inventor： Takehiro Shirai ,  Masayuki Iwase

IPC: H05K3/36

CPC classification number: G02B6/4201 ,  G02B6/3885 ,  G02B6/4277 ,  G02B6/428 ,  G02B6/4292 ,  H01L23/24 ,  H01L23/49861 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0219 ,  H05K1/056 ,  H05K3/06 ,  H05K3/44 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09754 ,  H05K2201/10121 ,  H05K2203/0323 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A printed wiring board includes a plurality of conductor plates that includes at least one conductor plate that is used as a lead for electrical connection with an external circuit, the conductor plates being separated spatially from one another; an insulating layer formed on or across the conductor plates or both on and across the conductor plates; and a plurality of wiring patterns formed on the insulating layer. At least one of the conductor plates is electrically connected with at least one of the wiring patterns through a via-hole.

Abstract translation: 印刷布线板包括多个导体板，其包括至少一个导体板，该导体板用作与外部电路电连接的引线，导体板彼此空间分离; 在导体板上或横跨导体板上形成绝缘层，或者两者在导体板上并跨过导体板; 以及形成在所述绝缘层上的多个布线图案。 至少一个导体板通过通孔与至少一个布线图形电连接。

公开(公告)号：US20100270066A1

公开(公告)日：2010-10-28

申请号：US11837181

申请日：2007-08-10

Applicant: Mumtaz Y. Bora ,  Ronald T. Mora

Inventor： Mumtaz Y. Bora ,  Ronald T. Mora

IPC: H01R12/04 ,  G06F17/50

CPC classification number: G06F17/50 ,  H05K1/115 ,  H05K3/0005 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09536 ,  H05K2201/096

Abstract: A printed circuit board (PCB) design system and method allows for PCB layouts that can be manufactured using a PCB manufacturing technology selected from multiple PCB manufacturing technologies with minimal or no modification to the PCB layout. Accordingly, a PCB layout of a PCB meets the requirements, or nearly meets the requirements, for multiple manufacturing technology design rules. In accordance with the exemplary embodiment, the PCB layout is designed to meet all design rules of a High Density Interconnect (HDI) manufacturing technology while minimizing requirements for layout changes when the PCB is manufactured using an Interstitial Via Hole (IVH) manufacturing technology. An IVH PCB includes a plurality of vias positioned within reserved via areas that form connections between at least some conductive elements on the board layers. The conductive elements and the plurality of vias form a layout such that a majority of reserved via areas, of all of the reserved via areas on the printed circuit board, are adequate to accommodate mechanically drilled vias manufactured in accordance with the HDI manufacturing technology.

Abstract translation: 印刷电路板（PCB）设计系统和方法允许使用从多个PCB制造技术中选择的PCB制造技术制造的PCB布局，对PCB布局进行最小化或不改变。 因此，PCB的PCB布局满足多个制造技术设计规则的要求，或几乎满足要求。 根据示例性实施例，PCB布局被设计成满足高密度互连（HDI）制造技术的所有设计规则，同时在使用间隙通孔（IVH）制造技术制造PCB时最小化对布局变化的要求。 IVH PCB包括多个通孔，其定位在保留的通孔区域内，所述通孔区域在板层上的至少一些导电元件之间形成连接。 导电元件和多个通孔形成布局，使得印刷电路板上的所有预留通孔区域中的大部分保留通孔区域足以容纳根据HDI制造技术制造的机械钻孔。

公开(公告)号：US07815968B2

公开(公告)日：2010-10-19

申请号：US12247894

申请日：2008-10-08

Applicant: Gareth Hougham ,  Leena Paivikki Buchwalter ,  Stephen L. Buchwalter ,  Jon Casey ,  Claudius Feger ,  Matteo Flotta ,  Jeffrey D. Gelmore ,  Kathleen C. Hinge ,  Anurag Jain ,  Sung K. Kang ,  John U. Knickerbocker

Inventor： Gareth Hougham ,  Leena Paivikki Buchwalter ,  Stephen L. Buchwalter ,  Jon Casey ,  Claudius Feger ,  Matteo Flotta ,  Jeffrey D. Gelmore ,  Kathleen C. Hinge ,  Anurag Jain ,  Sung K. Kang ,  John U. Knickerbocker

IPC: B05D3/12

CPC classification number: H05K3/4053 ,  B05D1/002 ,  H01L21/486 ,  H01L21/76898 ,  H05K2201/09509 ,  H05K2203/1554

Abstract: The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

Abstract translation: 本公开一般涉及半导体，集成电路，特别是但不限于，用于填充高纵横比通孔和沟槽的离心方法，其具有粉末，糊料，材料悬浮液，用作导电，结构 支撑或电子部件的保护构件。