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    MEMORY DEVICE FOR REDUCING A WRITE FAIL, A SYSTEM INCLUDING THE SAME, AND A METHOD THEREOF
    41.
    发明申请
    MEMORY DEVICE FOR REDUCING A WRITE FAIL, A SYSTEM INCLUDING THE SAME, AND A METHOD THEREOF 有权
    用于减少写入失败的存储器件，包括其的系统及其方法

    公开(公告)号：US20140068203A1

    公开(公告)日：2014-03-06

    申请号：US14013275

    申请日：2013-08-29

    申请人： JONG PIL SON ,  CHUL WOO PARK ,  HAK SOO YU ,  HONG SUN HWANG

    发明人： JONG PIL SON ,  CHUL WOO PARK ,  HAK SOO YU ,  HONG SUN HWANG

    IPC分类号： G06F3/06

    CPC分类号： G06F3/061 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0676 ,  G06F3/068 ,  G06F13/1642 ,  G11C7/00 ,  G11C7/1048 ,  G11C11/4076 ,  Y02D10/14

    摘要： A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to continuously perform a plurality of write commands on the memory device between an active command and a precharge command. In the memory system, when after a first write operation having a last write command of the plurality of write commands is performed and then the precharge command is issued, the last write command is issued for a second write operation after the precharge command. The first write operation and the second write operation write a same data to memory cells of plurality of memory cells having a same address.

    摘要翻译： 存储器系统包括存储器件和存储器控制器。 存储装置包括多个存储单元。 存储器控制器被配置为在活动命令和预充电命令之间在存储器设备上连续地执行多个写入命令。 在存储器系统中，当执行了具有多个写入命令的最后写入命令的第一次写入操作之后，然后执行预充电命令时，在预充电命令之后发出最后一个写入命令用于第二次写入操作。 第一写入操作和第二写入操作将相同的数据写入具有相同地址的多个存储单元的存储单元。

    SEMICONDUCTOR MEMORY DEVICES AND RELATED METHODS OF OPERATION
    42.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND RELATED METHODS OF OPERATION 有权
    半导体存储器件及其相关操作方法

    公开(公告)号：US20130322162A1

    公开(公告)日：2013-12-05

    申请号：US13907223

    申请日：2013-05-31

    申请人： YUN-SANG LEE ,  DONG-SEOK KANG ,  SANG-BEOM KANG ,  CHAN-KYUNG KIM ,  CHUL-WOO PARK ,  DONG-HYUN SOHN ,  HYUNG-ROK OH

    发明人： YUN-SANG LEE ,  DONG-SEOK KANG ,  SANG-BEOM KANG ,  CHAN-KYUNG KIM ,  CHUL-WOO PARK ,  DONG-HYUN SOHN ,  HYUNG-ROK OH

    IPC分类号： G11C11/16 ,  G11C7/12

    CPC分类号： G11C11/1653 ,  G11C7/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/1697

    摘要： A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE)

    摘要翻译： 半导体存储器件包括一个单元阵列，其包括一个或多个存储体组，其中一个或多个存储体组中的每个组包括多个存储体，并且多个存储体中的每一个存储体包括多个自旋传递转矩磁阻随机存取存储器（STT -MRAM）细胞。 半导体存储器件还包括用于向连接到多个STT-MRAM单元中的每一个的源极线施加电压的源极电压产生单元，以及用于对来自外部源的命令进行解码的命令解码器，以执行读取和 对多个STT-MRAM单元进行写入操作。 该命令包括行地址选通（RAS），列地址选通（CAS），片选信号（CS），写使能信号（WE）和时钟使能信号（CKE）的至少一个信号 ）

    Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same
    43.
    发明授权
    Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same 有权
    用于执行DRAM刷新操作的存储器电路，系统和模块及其操作方法

    公开(公告)号：US08588017B2

    公开(公告)日：2013-11-19

    申请号：US13236972

    申请日：2011-09-20

    申请人： Chul-woo Park ,  Young-hyun Jun ,  Joo-sun Choi ,  Hong-sun Hwang

    发明人： Chul-woo Park ,  Young-hyun Jun ,  Joo-sun Choi ,  Hong-sun Hwang

    IPC分类号： G11C29/00

    CPC分类号： G11C29/808 ,  G06F2213/0038 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/40626 ,  G11C2211/4062

    摘要： A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on the module and coupled to the plurality of dynamic memory devices, and can include a memory device operational parameter storage circuit that is configured to store memory device operational parameters for the respective regions to affect operation of the respective regions responsive to the command.

    摘要翻译： 存储器模块可以包括多个动态存储器设备，每个动态存储器设备可以包括其中具有其中各自区域的动态存储器单元阵列，其中多个动态存储器设备可被配置为响应于命令操作相应的区域。 DRAM管理单元可以在模块上并且耦合到多个动态存储器设备，并且可以包括存储器设备操作参数存储电路，其被配置为存储用于各个区域的存储器设备操作参数以影响相应区域的操作 命令。

    Semiconductor memory devices with mismatch cells
    47.
    发明授权
    Semiconductor memory devices with mismatch cells 有权
    具有不匹配单元的半导体存储器件

    公开(公告)号：US08199592B2

    公开(公告)日：2012-06-12

    申请号：US12591196

    申请日：2009-11-12

    申请人： Jin-Young Kim ,  Chul-Woo Park ,  Ki-Whan Song

    发明人： Jin-Young Kim ,  Chul-Woo Park ,  Ki-Whan Song

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4099 ,  G11C11/4091

    摘要： A semiconductor memory device having the mismatch cell makes a capacitance difference between a bit line pair relatively large during a read operation using at least one dummy memory cell as a mismatch cell selected together with a corresponding memory cell. Therefore, data of a semiconductor memory device may be detected more easily.

    摘要翻译： 具有不匹配单元的半导体存储器件在使用至少一个虚拟存储器单元作为与对应的存储器单元一起选择的不匹配单元的读取操作期间，位线对之间的电容差相对较大。 因此，可以更容易地检测半导体存储器件的数据。