公开(公告)号：US07524762B2

公开(公告)日：2009-04-28

申请号：US11773302

申请日：2007-07-03

申请人： Christophe Marcadal ,  Rongjun Wang ,  Hua Chung ,  Nirmalya Maity

发明人： Christophe Marcadal ,  Rongjun Wang ,  Hua Chung ,  Nirmalya Maity

IPC分类号： H01L21/44 ,  H01L21/07

CPC分类号： H01L29/495 ,  C23C16/18 ,  C23C16/30 ,  C23C16/45553 ,  H01L21/28079 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76864 ,  H01L29/4958 ,  H01L29/517

摘要： In one embodiment, a method for forming a tantalum-containing material on a substrate is provided which includes heating a liquid tantalum precursor containing tertiaryamylimido-tris(dimethylamido) tantalum (TAIMATA) to a temperature of at least 30° C. to form a tantalum precursor gas and exposing the substrate to a continuous flow of a carrier gas during an atomic layer deposition process. The method further provides exposing the substrate to the tantalum precursor gas by pulsing the tantalum precursor gas into the carrier gas and adsorbing the tantalum precursor gas on the substrate to form a tantalum precursor layer thereon. Subsequently, the tantalum precursor layer is exposed to at least one secondary element-containing gas by pulsing the secondary element-containing gas into the carrier gas while forming a tantalum barrier layer on the substrate. The tantalum barrier layer may contain tantalum, tantalum nitride, tantalum silicon nitride, tantalum boron nitride, tantalum phosphorous nitride or tantalum oxynitride.

摘要翻译： 在一个实施方案中，提供了一种用于在基底上形成含钽材料的方法，其包括将含有叔戊酰亚氨基 - 三（二甲基氨基）钽（TAIMATA）的液体钽前体加热至至少30℃的温度以形成钽 前体气体，并在原子层沉积过程中将衬底暴露于载气的连续流动。 该方法进一步通过将钽前体气体脉冲到载气中并将钽前驱体气体吸附在基底上以在其上形成钽前体层而使衬底暴露于钽前体气体。 随后，通过在衬底上形成钽阻挡层，将含二次元素的气体脉冲送入载气中，使钽前体层暴露于至少一个含二元素气体。 钽阻挡层可以包含钽，氮化钽，氮化钽，氮化硼，氮化钽或氮氧化钽。

公开(公告)号：US20090087982A1

公开(公告)日：2009-04-02

申请号：US12240822

申请日：2008-09-29

申请人： RONGJUN WANG ,  Hua Chung ,  Jick M. Yu ,  Praburam Gopalraja

发明人： RONGJUN WANG ,  Hua Chung ,  Jick M. Yu ,  Praburam Gopalraja

IPC分类号： H01L21/4763

CPC分类号： H01L21/28562 ,  C23C16/04 ,  C23C16/18 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76868 ,  H01L21/76871 ,  H01L2221/1089

摘要： Embodiments of the invention provide processes for selectively forming a ruthenium-containing film on a copper surface over exposed dielectric surfaces. Thereafter, a copper bulk layer may be deposited on the ruthenium-containing film. In one embodiment, a method for forming layers on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a copper-containing surface and a dielectric surface, exposing the substrate to a ruthenium precursor to selectively form a ruthenium-containing film over the copper-containing surface while leaving exposed the dielectric surface, and depositing a copper bulk layer over the ruthenium-containing film.

摘要翻译： 本发明的实施方案提供了在暴露的电介质表面上在铜表面上选择性地形成含钌膜的方法。 此后，可以将铜本体层沉积在含钌膜上。 在一个实施例中，提供了一种用于在衬底上形成层的方法，其包括将衬底定位在处理室内，其中衬底包含含铜表面和电介质表面，将衬底暴露于钌前体以选择性地形成钌 同时留下电介质表面，并在含钌膜上沉积铜体积层。

公开(公告)号：US20080190760A1

公开(公告)日：2008-08-14

申请号：US11838796

申请日：2007-08-14

申请人： XIANMIN TANG ,  Arvind Sundarrajan ,  Daniel Lubben ,  Qian Luo ,  Tza-Jing Gung ,  Anantha Subramani ,  Hua Chung ,  Xinyu Fu ,  Rongjun Wang ,  Yong Cao ,  Jick Yu ,  John Forster ,  Praburam Gopalraja

发明人： XIANMIN TANG ,  Arvind Sundarrajan ,  Daniel Lubben ,  Qian Luo ,  Tza-Jing Gung ,  Anantha Subramani ,  Hua Chung ,  Xinyu Fu ,  Rongjun Wang ,  Yong Cao ,  Jick Yu ,  John Forster ,  Praburam Gopalraja

IPC分类号： C23C14/32

CPC分类号： C23C14/165 ,  C23C14/046 ,  C23C14/358 ,  C23C14/5826 ,  C23C14/584 ,  H01J37/3408 ,  H01J37/3455 ,  H01L21/2855 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76877

摘要： An integrated copper deposition process, particularly useful for forming a copper seed layer in a narrow via prior to electrochemical plating of copper, including at least one cycle of sputter deposition of copper followed by sputter etching of the deposited copper, preferably performed in a same sputter chamber. The deposition is performed under conditions promoting high copper ionization fractions and strong wafer biasing to draw the copper ions into the via. The etching may be done with argon ions, preferably inductively excited by an RF coil around the chamber, or by copper ions, which may be formed with high target power and intense magnetron or by use of the RF coil. Two or more cycles of deposition/etch may be performed. A final flash deposition may be performed with high copper ionization and low wafer biasing.

摘要翻译： 一种集成的铜沉积工艺，特别适用于在铜的电化学电镀之前在窄通孔中形成铜籽晶层，包括至少一个铜的溅射沉积循环，然后溅射蚀刻沉积的铜，优选在相同的溅射 房间。 沉积在促进高铜离子化分数和强晶片偏置的条件下进行以将铜离子吸入通孔。 蚀刻可以用氩离子进行，优选地通过围绕室的RF线圈进行感应激励，或者通过可以用高目标功率和强磁控管形成的铜离子或通过使用RF线圈进行。 可以执行两个或更多个沉积/蚀刻循环。 最终的闪蒸沉积可以用高铜离子化和低晶片偏压进行。

公开(公告)号：US20060019495A1

公开(公告)日：2006-01-26

申请号：US11061039

申请日：2005-02-19

申请人： Christophe Marcadal ,  Rongjun Wang ,  Hua Chung ,  Nirmalya Maity

发明人： Christophe Marcadal ,  Rongjun Wang ,  Hua Chung ,  Nirmalya Maity

IPC分类号： H01L21/00

CPC分类号： H01L29/495 ,  C23C16/18 ,  C23C16/30 ,  C23C16/45553 ,  H01L21/28079 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76864 ,  H01L29/4958 ,  H01L29/517

摘要： In one example of the invention, a method for depositing a tantalum-containing material on a substrate in a process chamber is provided which includes exposing the substrate to a tantalum precursor that contains TAIMATA and to at least one secondary precursor to deposit a tantalum-containing film during an atomic layer deposition (ALD) process. The ALD process is repeated until the tantalum-containing film is deposited with a predetermined thickness. Usually, the TAIMATA is preheated prior pulsing the tantalum precursor into the process chamber. A metal layer, such as tungsten or copper, may be deposited on the tantalum-containing material. The tantalum-containing material may include tantalum, tantalum nitride, tantalum silicon nitride, tantalum boron nitride, tantalum phosphorous nitride or tantalum oxynitride. The tantalum-containing material may be deposited as a barrier or adhesion layer within a via or as a gate electrode material within a source/drain device.

摘要翻译： 在本发明的一个实例中，提供了一种用于在处理室中的衬底上沉积含钽材料的方法，其包括将衬底暴露于含有TAIMATA的钽前体和至少一种次级前体以沉积含钽的 在原子层沉积（ALD）过程中的膜。 重复ALD处理直到含有钽的膜以预定厚度沉积。 通常，TAIMATA在将钽前体脉冲进入处理室之前被预热。 诸如钨或铜的金属层可以沉积在含钽材料上。 含钽材料可以包括钽，氮化钽，氮化钽，氮化硼，氮化钽或氮氧化钽。 含钽材料可以作为阻挡层或粘附层沉积在源极/漏极器件内的通孔或栅电极材料内。

公开(公告)号：US20160293798A1

公开(公告)日：2016-10-06

申请号：US15183594

申请日：2016-06-15

申请人： Mingwei Zhu ,  Rongjun Wang ,  Nag B. Patibandla ,  Xianmin Tang ,  Vivek Agrawal ,  Cheng-Hsiung Tsai ,  Muhammad Rasheed ,  Dinesh Saigal ,  Praburam Gopal Raja ,  Omkaram Nalamasu ,  Anantha Subramani

发明人： Mingwei Zhu ,  Rongjun Wang ,  Nag B. Patibandla ,  Xianmin Tang ,  Vivek Agrawal ,  Cheng-Hsiung Tsai ,  Muhammad Rasheed ,  Dinesh Saigal ,  Praburam Gopal Raja ,  Omkaram Nalamasu ,  Anantha Subramani

IPC分类号： H01L33/12 ,  H01L33/32 ,  H01L33/00 ,  H01L33/06

CPC分类号： H01L33/12 ,  C30B23/02 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02631 ,  H01L21/02661 ,  H01L29/205 ,  H01L33/007 ,  H01L33/06 ,  H01L33/32

摘要： Fabrication of gallium nitride-based light devices with physical vapor deposition (PVD)-formed aluminum nitride buffer layers is described. Process conditions for a PVD AlN buffer layer are also described. Substrate pretreatments for a PVD aluminum nitride buffer layer are also described. In an example, a method of fabricating a buffer layer above a substrate involves pre-treating a surface of a substrate. The method also involves, subsequently, reactive sputtering an aluminum nitride (AlN) layer on the surface of the substrate from an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-based gas or plasma.

公开(公告)号：US09017533B2

公开(公告)日：2015-04-28

申请号：US12173198

申请日：2008-07-15

申请人： John C. Forster ,  Daniel J. Hoffman ,  John A. Pipitone ,  Xianmin Tang ,  Rongjun Wang

发明人： John C. Forster ,  Daniel J. Hoffman ,  John A. Pipitone ,  Xianmin Tang ,  Rongjun Wang

IPC分类号： C23C14/34 ,  H01J37/32 ,  H01J37/34

CPC分类号： H01J37/32165 ,  H01J37/32091 ,  H01J37/34 ,  H01J37/3444

摘要： In a physical vapor deposition plasma reactor, a multi-frequency impedance controller is coupled between RF ground and one of (a) the bias electrode, (b) the sputter target, the controller providing adjustable impedances at a first set of frequencies, said first set of frequencies including a first set of frequencies to be blocked and a first set of frequencies to be admitted. The first multi-frequency impedance controller includes a set of band pass filters connected in parallel and tuned to said first set of frequencies to be admitted, and a set of notch filters connected in series and tuned to said first set of frequencies to be blocked.

摘要翻译： 在物理气相沉积等离子体反应器中，多频阻抗控制器耦合在RF地与（a）偏置电极之一之间，（b）溅射靶，控制器在第一组频率处提供可调阻抗，所述第一 包括要阻止的第一组频率和要被接纳的第一组频率的频率集合。 第一多频阻抗控制器包括并联连接并被调谐到要被允许的所述第一组频率的一组带通滤波器，以及串联连接并被调谐到要被阻挡的所述第一组频率的一组陷波滤波器。

公开(公告)号：US08968537B2

公开(公告)日：2015-03-03

申请号：US13024198

申请日：2011-02-09

申请人： Muhammad M. Rasheed ,  Rongjun Wang

发明人： Muhammad M. Rasheed ,  Rongjun Wang

IPC分类号： H01J37/34 ,  C23C14/34 ,  C22C19/03 ,  C22C9/00 ,  C22C9/04

CPC分类号： C23C14/3407 ,  C22C9/00 ,  C22C9/04 ,  C22C19/03 ,  C23C14/3414 ,  H01J37/3426 ,  H01J37/3435

摘要： Embodiments of the invention provide sputtering targets utilized in physical vapor deposition (PVD) and methods to form such sputtering targets. In one embodiment, a sputtering target contains a target layer disposed on a backing plate, and a protective coating layer—usually containing a nickel material—covering and protecting a region of the backing plate that would otherwise be exposed to plasma during the PVD processes. In many examples, the target layer contains a nickel-platinum alloy, the backing plate contains a copper alloy (e.g., copper-zinc), and the protective coating layer contains metallic nickel. The protective coating layer eliminates the formation of highly conductive, copper contaminants typically derived by plasma erosion of the copper alloy contained within the exposed surfaces of the backing plate. Therefore, the substrates and the interior surfaces of the PVD chamber remain free of such copper contaminants during the PVD processes.

摘要翻译： 本发明的实施例提供了用于物理气相沉积（PVD）的溅射靶和形成这种溅射靶的方法。 在一个实施例中，溅射靶包含设置在背板上的目标层和通常包含镍材料覆盖层并保护背衬板的区域的保护涂层，否则在PVD工艺期间将暴露于等离子体的区域。 在许多实施例中，靶层含有镍 - 铂合金，背板含有铜合金（例如铜 - 锌），保护涂层含有金属镍。 保护涂层消除了形成高度导电的铜污染物，通常由包含在背板的暴露表面内的铜合金的等离子体侵蚀导致。 因此，在PVD工艺期间，PVD室的基板和内表面保持没有这种铜污染物。

公开(公告)号：US08920611B2

公开(公告)日：2014-12-30

申请号：US12173228

申请日：2008-07-15

申请人： John C. Forster ,  Daniel J. Hoffman ,  John A. Pipitone ,  Xianming Tang ,  Rongjun Wang

发明人： John C. Forster ,  Daniel J. Hoffman ,  John A. Pipitone ,  Xianming Tang ,  Rongjun Wang

IPC分类号： C23C14/34 ,  H01J37/34 ,  H01J37/32

CPC分类号： H01J37/34 ,  H01J37/32165 ,  H01J37/3444

摘要： The method of performing physical vapor deposition on a workpiece includes performing at least one of the following: (a) increasing ion density over a workpiece center while decreasing ion density over a workpiece edge by decreasing impedance to ground at a target source power frequency fs through a bias multi-frequency impedance controller relative to the impedance to ground at the source power frequency fs through the side wall; or (b) decreasing ion density over the workpiece center while increasing ion density over the workpiece edge by increasing the impedance to ground at fs through the bias multi-frequency impedance controller relative to the impedance to ground at fs through the side wall.

摘要翻译： 在工件上进行物理气相沉积的方法包括执行以下至少一个：（a）在工件中心上增加离子密度，同时通过减小目标源功率频率fs至 一个偏置多频阻抗控制器，相对于通过侧壁的源电源频率fs对地的阻抗; 或（b）通过在fs通过偏压多频阻抗控制器相对于通过侧壁的fs处的接地阻抗增加对fs的接地阻抗来增加工件边缘上的离子密度，从而降低工件中心的离子密度。

公开(公告)号：US08911601B2

公开(公告)日：2014-12-16

申请号：US13280771

申请日：2011-10-25

申请人： Muhammad Rasheed ,  Keith A. Miller ,  Rongjun Wang

发明人： Muhammad Rasheed ,  Keith A. Miller ,  Rongjun Wang

IPC分类号： C25B9/00 ,  C25B11/00 ,  C25B13/00 ,  C23C14/00 ,  B05C13/00 ,  B05C13/02 ,  B05C21/00 ,  C23C16/00 ,  C23C14/34 ,  C23C16/458 ,  C23C14/50 ,  C23C14/56 ,  H01L21/687

CPC分类号： C23C14/50 ,  C23C14/3407 ,  C23C14/564 ,  C23C16/4585 ,  H01L21/68735

摘要： Embodiments of the invention generally relate to a process kit for a semiconductor processing chamber, and a semiconductor processing chamber having a kit. More specifically, embodiments described herein relate to a process kit including a deposition ring and a pedestal assembly. The components of the process kit work alone, and in combination, to significantly reduce their effects on the electric fields around a substrate during processing.

摘要翻译： 本发明的实施例一般涉及用于半导体处理室的处理套件和具有套件的半导体处理室。 更具体地，本文所述的实施例涉及包括沉积环和基座组件的处理套件。 处理套件的组件单独工作，并且组合工作，以显着降低其在处理期间对基板周围的电场的影响。

公开(公告)号：US20130285065A1

公开(公告)日：2013-10-31

申请号：US13868385

申请日：2013-04-23

申请人： Mingwei Zhu ,  Rongjun Wang ,  Nag B. Patibandla ,  Xianmin Tang ,  Vivek Agrawal ,  Cheng-Hsiung Tsai ,  Muhammad Rasheed ,  Dinesh Saigal ,  Praburam Gopal Raja ,  Omkaram Nalamasu ,  Anantha Subramani

发明人： Mingwei Zhu ,  Rongjun Wang ,  Nag B. Patibandla ,  Xianmin Tang ,  Vivek Agrawal ,  Cheng-Hsiung Tsai ,  Muhammad Rasheed ,  Dinesh Saigal ,  Praburam Gopal Raja ,  Omkaram Nalamasu ,  Anantha Subramani

IPC分类号： H01L21/02 ,  H01L29/205

CPC分类号： H01L33/12 ,  C30B23/02 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02631 ,  H01L21/02661 ,  H01L29/205 ,  H01L33/007 ,  H01L33/06 ,  H01L33/32

摘要： Fabrication of gallium nitride-based light devices with physical vapor deposition (PVD)-formed aluminum nitride buffer layers is described. Process conditions for a PVD AlN buffer layer are also described. Substrate pretreatments for a PVD aluminum nitride buffer layer are also described. In an example, a method of fabricating a buffer layer above a substrate involves pre-treating a surface of a substrate. The method also involves, subsequently, reactive sputtering an aluminum nitride (AlN) layer on the surface of the substrate from an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-based gas or plasma.

摘要翻译： 描述了具有物理气相沉积（PVD）形成的氮化铝缓冲层的氮化镓基光器件的制造。 还描述了PVD AlN缓冲层的工艺条件。 还描述了PVD氮化铝缓冲层的基板预处理。 在一个实例中，在衬底上制造缓冲层的方法包括预处理衬底的表面。 该方法还涉及从容纳在具有氮基气体或等离子体的物理气相沉积（PVD）室中的含铝靶反应溅射基板表面上的氮化铝（AlN）层。