公开(公告)号：US07371971B2

公开(公告)日：2008-05-13

申请号：US11349188

申请日：2006-02-08

申请人： Yuichi Takayoshi ,  Kazushi Ichikawa ,  Toshiki Naito

发明人： Yuichi Takayoshi ,  Kazushi Ichikawa ,  Toshiki Naito

IPC分类号： H05K1/03

CPC分类号： H05K1/0269 ,  H05K1/111 ,  H05K3/303 ,  H05K3/3452 ,  H05K2201/094 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2203/163 ,  H05K2203/166 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155

摘要： A wired circuit board that can provide improved reliability on connection between the terminal portions and the external terminals while ensuring high productivity and cost reduction, and a production method thereof. After a conductive pattern 3 including terminal portions 6 to connect with external terminals 22 of an electronic component 21 and criterion marks 8 to determine presence or absence of an inhibitory portion 23 that may be formed due to formation of an insulating cover layer 4 to inhibit connection between the terminal portions 6 and the external terminals 22 are formed on the insulating base layer 2 simultaneously, the insulating cover layer 4 to cover the conductive pattern 3 and an opening 7 from which the terminal portions 6 and the criterion marks 8 are exposed is formed. Thereafter, the presence or absence of the inhibitory portion 23 is determined with reference to the criterion marks 8 exposed from the opening 7 of the insulating cover layer 4.

摘要翻译： 一种能够在确保高生产率和成本降低的同时，在端子部与外部端子之间的连接方面提高可靠性的布线电路板及其制造方法。 在包括与电子部件21的外部端子22连接的端子部分6的导电图案3和标准标记8之间以确定由于形成绝缘覆盖层4而形成的抑制部分23的存在或不存在以禁止连接 在绝缘基底层2上同时形成端子部分6和外部端子22之间，覆盖导电图案3的绝缘覆盖层4和端子部分6和标准标记8暴露的开口7形成 。 此后，参照从绝缘覆盖层4的开口部7露出的基准标记8来确定抑制部23的有无。

公开(公告)号：US07354697B2

公开(公告)日：2008-04-08

申请号：US10934703

申请日：2004-09-07

申请人： Toshiki Naito

发明人： Toshiki Naito

IPC分类号： G03F7/26

CPC分类号： H05K3/0082 ,  H05K3/0023 ,  H05K3/28 ,  H05K2201/0108 ,  H05K2203/0191 ,  H05K2203/1545 ,  Y10S430/162 ,  Y10T156/1089 ,  Y10T156/1092 ,  Y10T156/1093 ,  Y10T156/1095 ,  Y10T156/1097 ,  Y10T156/1098

摘要： The invention provides a process for producing a wiring circuit board, which comprises the steps of: (A) forming a conductor layer of a predetermined pattern on an insulating layer; (B) forming a photosensitive solder resist layer on the insulating layer and the patterned conductor layer formed on the insulating layer; (C) disposing a transparent protective film on the photosensitive solder resist layer; and (D) exposing the photosensitive solder resist layer to a light through the transparent protective film.

摘要翻译： 本发明提供一种制造布线电路板的方法，包括以下步骤：（A）在绝缘层上形成预定图案的导体层; （B）在绝缘层上形成感光性阻焊层和形成在绝缘层上的图案化导体层; （C）在感光性阻焊层上设置透明保护膜; 和（D）将光敏抗蚀剂层曝光通过透明保护膜。

公开(公告)号：US20070241764A1

公开(公告)日：2007-10-18

申请号：US11783999

申请日：2007-04-13

申请人： Toshiki Naito ,  Tetsuya Ohsawa ,  Kouji Kataoka

发明人： Toshiki Naito ,  Tetsuya Ohsawa ,  Kouji Kataoka

IPC分类号： G01R31/02

CPC分类号： H05K1/0269 ,  H05K1/056 ,  H05K3/0052 ,  H05K3/225 ,  H05K2201/0909 ,  H05K2201/09127 ,  H05K2201/0969 ,  H05K2201/09781 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/53022 ,  Y10T29/53026 ,  Y10T29/5303 ,  Y10T29/53035 ,  Y10T29/53039 ,  Y10T29/53043

摘要： A wired circuit board assembly sheet has a plurality of wired circuit boards, distinguishing marks for distinguishing defectiveness of the wired circuit boards, and a supporting sheet for supporting the plurality of wired circuit boards and the distinguishing marks. Each of the distinguishing marks has an indication portion for indicating a specified one of the wired circuit boards.

摘要翻译： 布线电路板组装片具有多个布线电路板，用于区分布线电路板的缺陷的区别标记和用于支撑多个布线电路板和区别标记的支撑片。 每个识别标记具有用于指示指定的一个有线电路板的指示部分。

公开(公告)号：US20070218781A1

公开(公告)日：2007-09-20

申请号：US11717706

申请日：2007-03-14

申请人： Takahiko Yokai ,  Toshiki Naito ,  Yasunari Ooyabu

发明人： Takahiko Yokai ,  Toshiki Naito ,  Yasunari Ooyabu

IPC分类号： H01R13/514

CPC分类号： H01R12/592 ,  H01R12/52 ,  H05K1/056 ,  H05K1/118 ,  H05K3/363 ,  H05K2201/10477 ,  H05K2203/041

摘要： A wired circuit board includes a metal supporting layer, an insulating layer formed on the metal supporting layer and a conductive pattern formed on the insulating layer, and having a terminal portion for connecting to an external terminal. The terminal portion is disposed at an end portion of the conductive pattern, supported on the insulating layer, and exposed from the metal supporting layer to have an end surface thereof used as a point of contact with the external terminal.

摘要翻译： 布线电路板包括金属支撑层，形成在金属支撑层上的绝缘层和形成在绝缘层上的导电图案，并且具有用于连接到外部端子的端子部分。 端子部分设置在导电图案的端部，被支撑在绝缘层上，并从金属支撑层露出，使其端面用作与外部端子的接触点。

公开(公告)号：US07205482B2

公开(公告)日：2007-04-17

申请号：US10680112

申请日：2003-10-08

申请人： Toshiki Naito ,  Hiroshi Yamazaki ,  Toshihiko Omote

发明人： Toshiki Naito ,  Hiroshi Yamazaki ,  Toshihiko Omote

IPC分类号： H05K1/03

CPC分类号： H01L23/49572 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K3/0097 ,  H05K2201/2009 ,  H05K2203/1545 ,  Y10T428/24777 ,  H01L2924/00

摘要： Electric conductor patterns having inner leads arranged at a pitch of not larger than 60 μm are formed on a front surface of an insulating layer of a tape carrier for TAB. A reinforcing layer of stainless steel foil is formed on a rear surface of the insulating layer so as to be extend along a lengthwise direction at opposite side edge portions in a widthwise direction of the insulating layer. Accordingly, both dimensional accuracy and positional accuracy can be improved at the time of carrying the tape carrier for TAB or at the time of mounting and bonding electronic parts though the insulating layer can be formed so as to be thin.

摘要翻译： 在TAB的带状载体的绝缘层的前表面上形成具有以不大于60μm的间距布置的内部引线的电导体图案。 在绝缘层的后表面上形成不锈钢箔的加强层，以沿着绝缘层的宽度方向的相对侧边缘部分的长度方向延伸。 因此，在携带用于TAB的带载体时或在安装和接合电子部件时，可以提高尺寸精度和位置精度，尽管绝缘层可以形成为薄。

公开(公告)号：US20060176069A1

公开(公告)日：2006-08-10

申请号：US11349188

申请日：2006-02-08

申请人： Yuichi Takayoshi ,  Kazushi Ichikawa ,  Toshiki Naito

发明人： Yuichi Takayoshi ,  Kazushi Ichikawa ,  Toshiki Naito

IPC分类号： G01R31/26

CPC分类号： H05K1/0269 ,  H05K1/111 ,  H05K3/303 ,  H05K3/3452 ,  H05K2201/094 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2203/163 ,  H05K2203/166 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155

摘要： A wired circuit board that can provide improved reliability on connection between the terminal portions and the external terminals while ensuring high productivity and cost reduction, and a production method thereof. After a conductive pattern 3 including terminal portions 6 to connect with external terminals 22 of an electronic component 21 and criterion marks 8 to determine presence or absence of an inhibitory portion 23 that may be formed due to formation of an insulating cover layer 4 to inhibit connection between the terminal portions 6 and the external terminals 22 are formed on the insulating base layer 2 simultaneously, the insulating cover layer 4 to cover the conductive pattern 3 and an opening 7 from which the terminal portions 6 and the criterion marks 8 are exposed is formed. Thereafter, the presence or absence of the inhibitory portion 23 is determined with reference to the criterion marks 8 exposed from the opening 7 of the insulating cover layer 4.

摘要翻译： 一种能够在确保高生产率和成本降低的同时，在端子部与外部端子之间的连接方面提高可靠性的布线电路板及其制造方法。 在包括与电子部件21的外部端子22连接的端子部分6的导电图案3和标准标记8之间以确定由于形成绝缘覆盖层4而形成的抑制部分23的存在或不存在以禁止连接 在绝缘基底层2上同时形成端子部分6和外部端子22之间，覆盖导电图案3的绝缘覆盖层4和端子部分6和标准标记8暴露的开口7形成 。 此后，参照从绝缘覆盖层4的开口部7露出的基准标记8来确定抑制部23的有无。

公开(公告)号：US20060093799A1

公开(公告)日：2006-05-04

申请号：US11259028

申请日：2005-10-27

申请人： Yasufumi Miyake ,  Kyouyuu Jo ,  Toshiki Naito ,  Yutaka Aoki

发明人： Yasufumi Miyake ,  Kyouyuu Jo ,  Toshiki Naito ,  Yutaka Aoki

IPC分类号： B32B3/00 ,  B32B18/00

CPC分类号： H05K1/0346 ,  B32B15/08 ,  B32B27/281 ,  B32B2250/44 ,  B32B2255/06 ,  B32B2255/10 ,  B32B2255/26 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2307/714 ,  B32B2457/08 ,  C08G61/122 ,  H05K1/0333 ,  H05K1/0393 ,  Y10T428/24917 ,  Y10T428/24926

摘要： A wired circuit board having good alkali resistance as well as good flexibility. The wired circuit board comprising an insulating base layer 21, a conductor layer 22 laminated on the insulating layer 21, and an insulating cover layer 23 formed on the insulating base layer 21 to cover the conductor layer 22, wherein at least the insulating base layer 21 is formed from a resin having a repeated unit expressed by at least either the following general formula (1) or (2), and a weight-average molecular weight in the range of 0.1×105 to 1.5×105: Chemical Formula (1) (n represents a degree of polymerization) Chemical Formula (2) (m represents a degree of polymerization)

摘要翻译： 具有良好耐碱性和良好柔性的有线电路板。 布线电路板包括绝缘基底层21，层叠在绝缘层21上的导体层22和形成在绝缘基底层21上以覆盖导体层22的绝缘覆盖层23，其中至少绝缘基底层21 由具有由至少以下通式（1）或（2）表示的重复单元的树脂形成，并且重均分子量在0.1×10 5至1.5×10 5范围内 化学式（1）（n表示聚合度）化学式（2）（m表示聚合度）

公开(公告)号：US20050115066A1

公开(公告)日：2005-06-02

申请号：US10992009

申请日：2004-11-19

申请人： Mitsuru Honjo ,  Toshiki Naito

发明人： Mitsuru Honjo ,  Toshiki Naito

IPC分类号： H05K3/24 ,  H05K3/06 ,  H05K3/10 ,  H05K3/02

CPC分类号： H05K3/108 ,  H05K3/062 ,  H05K2201/0347 ,  H05K2203/0542 ,  H05K2203/0597 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A production method of a wired circuit board that can prevent corrosion of a first thin metal film inwardly of a conductor layer, which is due to the forming of an undercut portion caused by a skirt portion of a plating resist, to prevent the peeling of a wiring circuit pattern. An insulating base layer 1 is prepared, first, and, then, a first thin metal film 2 is formed on the insulating base layer 1. Then, a plating resist 3 is formed in a reversal pattern to a wiring circuit pattern 4 on the first thin metal film 2, and a conductor layer 6 is formed in the wiring circuit pattern 4 on the first thin metal film 2 exposed form the plating resist 3. Thereafter, the plating resist 3 is removed and, then, a second thin metal film 8 is formed on the conductor layer 6 and first thin metal film 2. Thereafter, the second thin metal film 8 is removed. Then, all portions of the first thin metal layer 2, except portions thereof where the conductor layer 6 is formed, are removed. The flexible wired circuit board is produced by the processes described above.

摘要翻译： 一种布线电路板的制造方法，其能够防止由电镀抗蚀剂的裙部形成的底切部形成导体层内部的第一薄金属膜的腐蚀，防止剥离 布线电路图案。 首先制备绝缘基底层1，然后在绝缘基底层1上形成第一薄金属膜2。 然后，以与第一薄金属膜2上的布线电路图案4相反的方式形成电镀抗蚀剂3，并且在布线电路图案4中形成导体层6，第一薄金属膜2暴露于镀层 抗拒3。 此后，除去电镀抗蚀剂3，然后在导体层6和第一薄金属膜2上形成第二薄金属膜8。 此后，去除第二薄金属膜8。 然后，除去第一薄金属层2的除了形成导体层6的部分之外的所有部分。 柔性布线电路板通过上述工艺制造。

公开(公告)号：US06889432B2

公开(公告)日：2005-05-10

申请号：US10358219

申请日：2003-02-05

申请人： Toshiki Naito ,  Yoshifumi Shinogi ,  Daisuke Uenda

发明人： Toshiki Naito ,  Yoshifumi Shinogi ,  Daisuke Uenda

IPC分类号： H05K1/02 ,  H05K3/06 ,  H05K3/10 ,  H05K3/18 ,  H05K3/38 ,  H05K3/42 ,  H01K3/10

CPC分类号： H05K1/0265 ,  H05K3/064 ,  H05K3/108 ,  H05K3/388 ,  H05K3/421 ,  H05K3/426 ,  H05K3/427 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0574 ,  H05K2203/0577 ,  H05K2203/1394 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T428/24917

摘要： A method for manufacturing a double-sided circuit board from a board material having a first electric conductor layer and a first electrically insulating layer, including the steps of: making conduction holes in the board material so as to penetrate only the first electrically insulating layer or both the first electrically insulating layer and the first electric conductor layer; forming an electrically conductive thin-film layer on a surface of the first electrically insulating layer and wall surfaces of the conduction holes; forming a second electrically insulating layer on the electrically conductive thin-film layer; forming a first electric conductor wiring by electroplating on predetermined portions of the electrically conductive thin-film layer; covering the first electric conductor wiring with a chemical-resistant film; forming a second electric conductor wiring by chemically dissolving a predetermined portion of another surface of the first electric conductor layer; and removing the second electrically insulating layer and the film.

摘要翻译： 一种从具有第一导电体层和第一电绝缘层的基板材料制造双面电路板的方法，包括以下步骤：在基板材料中形成导电孔，以仅穿透第一电绝缘层或 第一电绝缘层和第一导电体层; 在第一电绝缘层的表面和导电孔的壁表面上形成导电薄膜层; 在所述导电薄膜层上形成第二电绝缘层; 通过电镀在导电薄膜层的预定部分上形成第一导电体布线; 用耐化学性膜覆盖第一导电线; 通过化学溶解所述第一导电体层的另一个表面的预定部分来形成第二导电体布线; 以及去除所述第二电绝缘层和所述膜。

公开(公告)号：US6011310A

公开(公告)日：2000-01-04

申请号：US722321

申请日：1996-09-27

申请人： Toshiki Naito ,  Kazuo Ouchi

发明人： Toshiki Naito ,  Kazuo Ouchi

IPC分类号： H01L21/60 ,  H01L23/498 ,  H01L23/50 ,  H05K3/40 ,  H05K3/42 ,  H01L23/48 ,  H01L23/053 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/81 ,  H01L23/4985 ,  H05K3/4007 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/1572 ,  H05K3/423

摘要： Disclosed are a film carrier comprising an insulating layer having laid therein an electrically conductive circuit such that the circuit is not exposed on the surface thereof, wherein conductive passages from the conductive circuit to one surface of the insulating layer are formed in the insulating layer and via holes from said conductive circuit to the other surface of the insulating layer are formed and a semiconductor device prepared by mounting a semiconductor element on the insulating layer of the film carrier. The film carrier can sufficiently correspond to pitch-fining and high-density mounting of a semiconductor element wiring, can surely perform the connecting operation of inner lead bonding and outer lead bonding and gives the mounting area of as small as possible.

摘要翻译： 公开了一种薄膜载体，其包括绝缘层，其中放置有导电电路，使得该电路不在其表面上露出，其中从导电电路到绝缘层的一个表面的导电通道形成在绝缘层中，并且经由 形成从所述导电电路到绝缘层的另一表面的孔，以及通过将半导体元件安装在膜载体的绝缘层上而制备的半导体器件。 薄膜载体可以充分地对应于半导体元件布线的节距精细和高密度安装，可以可靠地执行内引线接合和外引线接合的连接操作，并且使安装面积尽可能小。