公开(公告)号：US08030772B2

公开(公告)日：2011-10-04

申请号：US12124113

申请日：2008-05-20

申请人： David E. Lazovsky ,  Sandra G. Malhotra ,  Thomas R. Boussie

发明人： David E. Lazovsky ,  Sandra G. Malhotra ,  Thomas R. Boussie

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/7685 ,  B82Y30/00 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/288 ,  H01L21/31 ,  H01L21/76834

摘要： Devices are presented including: a substrate including a dielectric region and a conductive region; a molecular self-assembled layer selectively formed on the dielectric region; and a capping layer formed on the conductive region, where the capping layer is an electrically conductive material such as: an alloy of cobalt and boron material, an alloy of cobalt, tungsten, and phosphorous material, an alloy of nickel, molybdenum, and phosphorous. In some embodiments, devices are presented where the molecular self-assembled layer includes one or more of a polyelectrolyte, a dendrimer, a hyper-branched polymer, a polymer brush, a block co-polymer, and a silane-based material where the silane-based material includes one or more hydrolysable substituents of a general formula RnSiX4-n, where R is: an alkyl, a substituted alkyl, a fluoroalkyl, an aryl, a substituted aryl, and a fluoroaryl, and where X is: a halo, an alkoxy, an aryloxy, an amino, an octadecyltrichlorosilane, and an aminopropyltrimethoxysilane.

摘要翻译： 本发明提供了包括：包括电介质区域和导电区域的衬底; 选择性地形成在电介质区域上的分子自组装层; 以及形成在导电区域上的覆盖层，其中覆盖层是导电材料，例如钴和硼材料的合金，钴，钨和磷材料的合金，镍，钼和磷的合金 。 在一些实施方案中，存在装置，其中分子自组装层包括聚电解质，树枝状聚合物，超支化聚合物，聚合物刷，嵌段共聚物和硅烷基材料中的一种或多种，​​其中硅烷 基团的材料包括一个或多个通式R n SiX 4-n的可水解取代基，其中R是：烷基，取代的烷基，氟代烷基，芳基，取代的芳基和氟代芳基，其中X是：卤素， 烷氧基，芳氧基，氨基，十八烷基三氯硅烷和氨基丙基三甲氧基硅烷。

公开(公告)号：US07977153B2

公开(公告)日：2011-07-12

申请号：US12967530

申请日：2010-12-14

申请人： Pragati Kumar ,  Sandra G. Malhotra ,  Sean Barstow ,  Tony Chiang

发明人： Pragati Kumar ,  Sandra G. Malhotra ,  Sean Barstow ,  Tony Chiang

IPC分类号： H01L21/00 ,  H01L21/16 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L45/1625 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1641

摘要： Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed from resistive-switching metal oxide layers. Metal oxide layers may be formed using sputter deposition at relatively low sputtering powers, relatively low duty cycles, and relatively high sputtering gas pressures. Dopants may be incorporated into a base oxide layer at an atomic concentration that is less than the solubility limit of the dopant in the base oxide. At least one oxidation state of the metal in the base oxide is preferably different than at least one oxidation state of the dopant. The ionic radius of the dopant and the ionic radius of the metal may be selected to be close to each other. Annealing and oxidation operations may be performed on the resistive switching metal oxides. Bistable metal oxides with relatively large resistivities and large high-state-to-low state resistivity ratios may be produced.

摘要翻译： 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以由电阻式开关金属氧化物层形成。 金属氧化物层可以使用相对低的溅射功率，相对低的占空比和较高的溅射气体压力的溅射沉积形成。 掺杂剂可以以小于基底氧化物中的掺杂剂的溶解度极限的原子浓度结合到基底氧化物层中。 基底氧化物中的金属的至少一种氧化态优选不同于掺杂剂的至少一种氧化态。 可以选择掺杂剂的离子半径和金属的离子半径彼此接近。 可以对电阻式开关金属氧化物进行退火和氧化操作。 可以制造具有相对较大的电阻率和大的高 - 低 - 电阻率比的双稳态金属氧化物。

公开(公告)号：US20110021015A1

公开(公告)日：2011-01-27

申请号：US12815206

申请日：2010-06-14

申请人： David E. Lazovsky ,  Sandra G. Malhotra ,  Thomas R. Boussie

发明人： David E. Lazovsky ,  Sandra G. Malhotra ,  Thomas R. Boussie

IPC分类号： H01L21/44

CPC分类号： H01L21/76829 ,  B82Y30/00 ,  H01L21/02183 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76849

摘要： A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g., a cobalt alloy, a nickel alloy, tungsten, tantalum, tantalum nitride), a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

摘要翻译： 在电子器件的电介质区域上形成掩模层，使得在随后在由电介质区域分离的电子器件的导电区域上形成覆盖层时，掩模层阻止在其上形成覆盖层材料 在电介质区域。 可以选择性地在导电区域或非选择性地形成覆盖层; 在任一情况下（特别是在后者中），可以随后去除在电介质区域上形成的覆盖层材料，从而确保覆盖层材料仅在导电区域上形成。 可以使用诸如硅烷基SAM之类的硅烷基材料来形成掩模层。 覆盖层可以由导电材料（例如，钴合金，镍合金，钨，钽，氮化钽），半导体材料或电绝缘材料形成，并且可以使用任何适当的工艺形成，包括 常规沉积工艺如无电沉积，化学气相沉积，物理气相沉积或原子层沉积。

公开(公告)号：US07863087B1

公开(公告)日：2011-01-04

申请号：US12114655

申请日：2008-05-02

申请人： Pragati Kumar ,  Sandra G. Malhotra ,  Sean Barstow ,  Tony Chiang

发明人： Pragati Kumar ,  Sandra G. Malhotra ,  Sean Barstow ,  Tony Chiang

IPC分类号： H01L21/00 ,  H01L21/16 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L45/1625 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1641

摘要： Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed from resistive-switching metal oxide layers. Metal oxide layers may be formed using sputter deposition at relatively low sputtering powers, relatively low duty cycles, and relatively high sputtering gas pressures. Dopants may be incorporated into a base oxide layer at an atomic concentration that is less than the solubility limit of the dopant in the base oxide. At least one oxidation state of the metal in the base oxide is preferably different than at least one oxidation sate of the dopant. The ionic radius of the dopant and the ionic radius of the metal may be selected to be close to each other. Annealing and oxidation operations may be performed on the resistive switching metal oxides. Bistable metal oxides with relatively large resistivities and large high-state-to-low state resistivity ratios may be produced.

摘要翻译： 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以由电阻式开关金属氧化物层形成。 金属氧化物层可以使用相对低的溅射功率，相对低的占空比和较高的溅射气体压力的溅射沉积形成。 掺杂剂可以以小于基底氧化物中的掺杂剂的溶解度极限的原子浓度结合到基底氧化物层中。 基底氧化物中金属的至少一种氧化态优选不同于掺杂剂的至少一种氧化态。 可以选择掺杂剂的离子半径和金属的离子半径彼此接近。 可以对电阻式开关金属氧化物进行退火和氧化操作。 可以制造具有相对较大的电阻率和大的高 - 低 - 电阻率比的双稳态金属氧化物。

公开(公告)号：US20080237053A1

公开(公告)日：2008-10-02

申请号：US12127477

申请日：2008-05-27

申请人： Panayotis Andricacos ,  Steven H. Boettcher ,  Sandra G. Malhotra ,  Milan Paunovic ,  Craig Ransom

发明人： Panayotis Andricacos ,  Steven H. Boettcher ,  Sandra G. Malhotra ,  Milan Paunovic ,  Craig Ransom

IPC分类号： C25D5/34

CPC分类号： C25D3/562 ,  C25D7/12 ,  H01L21/2885 ,  H01L21/76846

摘要： An interconnection structure comprising a substrate having a dielectric layer with a via opening therein; wherein the opening has an underlayer of cobalt and/or nickel therein, barrier layer of an alloy of cobalt and/or nickel; and tungsten is provided.

摘要翻译： 一种互连结构，包括其中具有通孔开口的介电层的基板; 其中所述开口具有其中的钴和/或镍的底层，钴和/或镍的合金的阻挡层; 并提供钨。

公开(公告)号：US06989321B2

公开(公告)日：2006-01-24

申请号：US10673908

申请日：2003-09-30

申请人： Hideaki Yamasaki ,  Tsukasa Matsuda ,  Atsushi Gomi ,  Tatsuo Hatano ,  Masahito Sugiura ,  Yumiko Kawano ,  Gert J Leusink ,  Fenton R McFeely ,  Sandra G. Malhotra

发明人： Hideaki Yamasaki ,  Tsukasa Matsuda ,  Atsushi Gomi ,  Tatsuo Hatano ,  Masahito Sugiura ,  Yumiko Kawano ,  Gert J Leusink ,  Fenton R McFeely ,  Sandra G. Malhotra

IPC分类号： H01L21/20 ,  H01L21/44

CPC分类号： C23C16/16 ,  H01L21/28556

摘要： A method for depositing metal layers on semiconductor substrates by a thermal chemical vapor deposition (TCVD) process includes introducing a process gas containing a metal carbonyl precursor in a process chamber and depositing a metal layer on a substrate. The TCVD process utilizes a short residence time for the gaseous species in the processing zone above the substrate to form a low-resistivity metal layer. In one embodiment of the invention, the metal carbonyl precursor can be selected from at least one of W(CO)6, Ni(CO)4, Mo(CO)6, Co2(CO)8, Rh4(CO)12, Re2(CO)10, Cr(CO)6, and Ru3(CO)12 precursors. In another embodiment of the invention, a method is provided for depositing low-resistivity W layers at substrate temperatures below about 500° C., by utilizing a residence time less than about 120 msec.

摘要翻译： 通过热化学气相沉积（TCVD）方法在金属层上沉积金属层的方法包括在处理室中引入含有羰基金属前驱体的工艺气体并在基底上沉积金属层。 TCVD工艺利用在衬底上方的处理区域中的气态物质的短暂停留时间以形成低电阻率金属层。 在本发明的一个实施方案中，羰基金属前体可以选自W（CO）6，Ni（CO）4，Mo（CO） CO 2，CO 2，CO 2，CO 2，CO 2，CO 2，CO 2， Re（CO）10，Cr（CO）6和Ru 3（CO）3， 12个前体。 在本发明的另一个实施例中，提供了一种通过利用小于约120毫秒的停留时间在低于约500℃的衬底温度下沉积低电阻W层的方法。

公开(公告)号：US06975032B2

公开(公告)日：2005-12-13

申请号：US10319967

申请日：2002-12-16

申请人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

发明人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

公开(公告)号：US06792075B2

公开(公告)日：2004-09-14

申请号：US10225534

申请日：2002-08-21

申请人： Krzysztof J. Kozaczek ,  David S. Kurtz ,  Paul R. Moran ,  Roger I. Martin ,  Patrick W. Dehaven ,  Kenneth P. Rodbell ,  Sandra G. Malhotra

发明人： Krzysztof J. Kozaczek ,  David S. Kurtz ,  Paul R. Moran ,  Roger I. Martin ,  Patrick W. Dehaven ,  Kenneth P. Rodbell ,  Sandra G. Malhotra

IPC分类号： G01N2320

CPC分类号： G01N23/20 ,  G01B15/02

摘要： An apparatus and method for mapping film thickness of one or more textured polycrystalline thin films. Multiple sample films of known thickness are provided. Each sample film is irradiated by x-ray at a measurement point to generate a diffraction image that captures a plurality of diffraction arcs. Texture information (i.e., pole densities) of the sample film, is calculated based on incomplete pole figures collected on the diffraction image and used to correct the x-ray diffraction intensities from such sample. The corrected diffraction intensities are integrated for each sample film, and then used for constructing a calibration curve that correlates diffraction intensities with respective known film thickness of the sample films. The film thickness of a textured polycrystalline thin film of unknown thickness can therefore be mapped on such calibration curve, using a corrected and integrated diffraction intensity obtained for such thin film of unknown thickness.

摘要翻译： 一种用于映射一个或多个纹理多晶薄膜的膜厚度的装置和方法。 提供了已知厚度的多个样品膜。 每个样品膜在测量点用X射线照射，以产生捕获多个衍射弧的衍射图像。 基于在衍射图像上收集的不完全的极数计算样品膜的纹理信息（即极点密度），并用于校正这些样品的X射线衍射强度。 对每个样品膜整合校正的衍射强度，然后用于构建将衍射强度与样品膜的已知膜厚度相关联的校准曲线。 因此，可以使用未知厚度的薄膜获得的校正和积分的衍射强度，将这种具有未知厚度的纹理多晶薄膜的膜厚度映射到这种校准曲线上。

公开(公告)号：US06153935A

公开(公告)日：2000-11-28

申请号：US409244

申请日：1999-09-30

申请人： Daniel C. Edelstein ,  Timothy J. Dalton ,  John G. Gaudiello ,  Mahadevaiyer Krishnan ,  Sandra G. Malhotra ,  Maurice McGlashan-Powell ,  Eugene J. O'Sullivan ,  Carlos J. Sambucetti

发明人： Daniel C. Edelstein ,  Timothy J. Dalton ,  John G. Gaudiello ,  Mahadevaiyer Krishnan ,  Sandra G. Malhotra ,  Maurice McGlashan-Powell ,  Eugene J. O'Sullivan ,  Carlos J. Sambucetti

IPC分类号： H01L21/30 ,  H01L21/288 ,  H01L21/321 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76849 ,  H01L21/288 ,  H01L21/3212 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76835

摘要： A damascene interconnect containing a dual etch stop/diffusion barrier. The conductive material of the damascene interconnect is capped with a conductive metal diffusion barrier cap, typically using electroless deposition, and, optionally, with a dielectric etch-stop layer. An optional chemical mechanical polish-stop layer may also be present. The different methods of the invention allow the CMP stop, reactive-ion etch stop, and metal diffusion barrier requirements of the different layers to be decoupled. A preferred conductive material is copper.

摘要翻译： 包含双蚀刻停止/扩散屏障的镶嵌互连。 镶嵌互连的导电材料用导电金属扩散阻挡盖（通常使用无电沉积）和可选地与电介质蚀刻停止层封盖。 还可以存在任选的化学机械抛光 - 停止层。 本发明的不同方法允许不同层的CMP停止，反应离子蚀刻停止和金属扩散阻挡层要求被去耦合。 优选的导电材料是铜。

公开(公告)号：US08772123B2

公开(公告)日：2014-07-08

申请号：US13237065

申请日：2011-09-20

申请人： Hanhong Chen ,  Sandra G. Malhotra ,  Wim Deweerd ,  Hiroyuki Ode

发明人： Hanhong Chen ,  Sandra G. Malhotra ,  Wim Deweerd ,  Hiroyuki Ode

IPC分类号： H01L21/20

CPC分类号： H01L28/40 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L27/1085 ,  H01L28/60

摘要： A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic % and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO2 and ZrO2 and further comprises a dopant of Al2O3. In some embodiments, the compound high k dielectric material comprises an admixture of TiO2 and HfO2 and further comprises a dopant of Al2O3.

摘要翻译： 用于形成具有低漏电流和低EOT的DRAM MIM电容器堆叠的方法涉及使用复合高k电介质材料。 电介质材料还包括掺杂剂。 复合高k介电材料的一个组分以约30原子％至约80原子％，更优选约40原子％至约60原子％的浓度存在。 在一些实施方案中，化合物高k介电材料包含TiO 2和ZrO 2的合金，并且还包含Al 2 O 3的掺杂剂。 在一些实施方案中，化合物高k介电材料包含TiO 2和HfO 2的混合物，并且还包含Al 2 O 3的掺杂剂。