公开(公告)号：US20180350780A1

公开(公告)日：2018-12-06

申请号：US16047688

申请日：2018-07-27

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Holger Doepke ,  Olaf Hohlfeld ,  Michael Juerss

IPC: H01L25/07

CPC classification number: H01L25/072 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/552 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/03462 ,  H01L2224/05647 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48491 ,  H01L2224/73265 ,  H01L2224/83951 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18301 ,  H05K3/282 ,  H05K3/284 ,  H05K2201/09872 ,  H05K2203/1316 ,  H05K2203/1322 ,  H05K2203/1377 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: An electronic device package includes a semiconductor chip having a contact pad on a main face of the semiconductor chip, a contact element disposed on the contact pad, a dielectric layer disposed on the semiconductor chip and the contact element, and an encapsulant disposed onto the dielectric layer.

公开(公告)号：US09595502B2

公开(公告)日：2017-03-14

申请号：US14926258

申请日：2015-10-29

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Edward Fuergut ,  Horst Groeninger ,  Juergen Hoegerl

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/433 ,  H01L29/739 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/72 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3185 ,  H01L23/433 ,  H01L24/83 ,  H01L29/7393 ,  H01L2924/351

Abstract: A semiconductor assembly is described. In accordance with one example of the invention, the semiconductor assembly comprises a semiconductor body, a top main electrode arranged on a top side, a bottom main electrode arranged on an underside, and a control electrode arranged on the top side. The semiconductor assembly further includes a spring element for the pressure contacting of the control electrode with a pressure force generated by the spring element.

Abstract translation: 描述半导体组件。 根据本发明的一个示例，半导体组件包括半导体主体，布置在顶侧的顶部主电极，设置在下侧的底部主电极和布置在顶侧的控制电极。 半导体组件还包括用于使控制电极与弹簧元件产生的压力的压力接触的弹簧元件。

公开(公告)号：US20160126211A1

公开(公告)日：2016-05-05

申请号：US14926258

申请日：2015-10-29

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Edward Fuergut ,  Horst Groeninger ,  Juergen Hoegerl

IPC: H01L23/00

CPC classification number: H01L24/72 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3185 ,  H01L23/433 ,  H01L24/83 ,  H01L29/7393 ,  H01L2924/351

Abstract: A semiconductor assembly is described. In accordance with one example of the invention, the semiconductor assembly comprises a semiconductor body, a top main electrode arranged on a top side, a bottom main electrode arranged on an underside, and a control electrode arranged on the top side. The semiconductor assembly further includes a spring element for the pressure contacting of the control electrode with a pressure force generated by the spring element.

Abstract translation: 描述半导体组件。 根据本发明的一个示例，半导体组件包括半导体主体，布置在顶侧的顶部主电极，设置在下侧的底部主电极和布置在顶侧的控制电极。 半导体组件还包括用于使控制电极与弹簧元件产生的压力的压力接触的弹簧元件。

公开(公告)号：US20150130048A1

公开(公告)日：2015-05-14

申请号：US14077694

申请日：2013-11-12

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Gottfried Beer ,  Magdalena Hoier

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L23/3107 ,  H01L23/3135 ,  H01L24/24 ,  H01L24/82 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/12043 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor package includes a mold body having a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces, a first semiconductor module including a plurality of first semiconductor chips and a first encapsulation layer disposed above the first semiconductor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of second semiconductor channels and a second encapsulation layer disposed above the second semiconductor channels. The semiconductor package further includes a plurality of external connectors extending through one or more of the side faces of the mold body.

Abstract translation: 半导体封装包括具有第一主面，与第一主面相对的第二主面和连接第一主面和第二主面的侧面的模体，包括多个第一半导体芯片的第一半导体模块和第一封装层 设置在第一半导体芯片上方，以及设置在第一半导体模块上方的第二半导体模块。 第二半导体模块包括多个第二半导体沟道和设置在第二半导体沟道上方的第二封装层。 半导体封装还包括延伸穿过模具主体的一个或多个侧面的多个外部连接器。

公开(公告)号：US20150054159A1

公开(公告)日：2015-02-26

申请号：US13974583

申请日：2013-08-23

Applicant: Infineon Technologies AG

Inventor： Juergen Hoegerl ,  Edward Fuergut ,  Gottfried Beer ,  Olaf Hohlfeld

IPC: H01L23/522 ,  H01L23/28 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L21/561 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/09 ,  H01L24/24 ,  H01L24/29 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/89 ,  H01L24/92 ,  H01L25/18 ,  H01L27/12 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2413 ,  H01L2224/24137 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/92244 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014

Abstract: The semiconductor module includes a carrier, a plurality of semiconductor transistor chips disposed on the carrier, a plurality of semiconductor diode chips disposed on the carrier, an encapsulation layer disposed above the semiconductor transistor chips and the semiconductor diode chips, and a metallization layer disposed above the encapsulation layer. The metallization layer includes a plurality of metallic areas forming electrical connections between selected ones of the semiconductor transistor chips and the semiconductor diode chips.

Abstract translation: 半导体模块包括载体，设置在载体上的多个半导体晶体管芯片，设置在载体上的多个半导体二极管芯片，设置在半导体晶体管芯片和半导体二极管芯片上方的封装层以及设置在半导体二极管芯片上方的金属化层 封装层。 金属化层包括形成半导体晶体管芯片中选定的半导体晶体管芯片和半导体二极管芯片之间的电连接的多个金属区域。

公开(公告)号：US08963321B2

公开(公告)日：2015-02-24

申请号：US13749006

申请日：2013-01-24

Applicant: Infineon Technologies AG

Inventor： Andreas Lenniger ,  Andre Uhlemann ,  Olaf Hohlfeld

IPC: H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L21/00 ,  H01L23/367 ,  H01L21/50 ,  H01L23/473 ,  H01L23/00 ,  H01L25/07 ,  H01L23/24 ,  H01L23/373 ,  H01L23/31 ,  H01L23/40

CPC classification number: H01L23/367 ,  H01L21/50 ,  H01L23/24 ,  H01L23/3135 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/4006 ,  H01L23/473 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/072 ,  H01L2224/291 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48132 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/85205 ,  H01L2224/8584 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2224/83205 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor device includes a semiconductor chip joined with a substrate and a base plate joined with the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure. The second metal layer has a sub-layer that has no pins and no pin-fins. The first metal layer has a first thickness and the sub-layer has a second thickness. The ratio between the first thickness and the second thickness is at least 4:1.

Abstract translation: 半导体器件包括与衬底连接的半导体芯片和与衬底接合的基板。 基板包括包覆到第二金属层的第一金属层。 第二金属层变形以提供销鳍或翅片冷却结构。 第二金属层具有没有引脚而没有引脚鳍的子层。 第一金属层具有第一厚度，并且子层具有第二厚度。 第一厚度与第二厚度之比至少为4:1。

公开(公告)号：US11715647B2

公开(公告)日：2023-08-01

申请号：US17342975

申请日：2021-06-09

Applicant: Infineon Technologies AG

Inventor： Fabian Craes ,  Carsten Ehlers ,  Olaf Hohlfeld ,  Ulrich Wilke

IPC: H01L21/54 ,  H01L21/48 ,  H01L21/308 ,  H01L21/56 ,  H01L21/67 ,  H01L23/00

CPC classification number: H01L21/54 ,  H01L21/308 ,  H01L21/4857 ,  H01L21/56 ,  H01L21/67069 ,  H01L24/27

Abstract: A method includes forming a first electrically conductive layer on a first side of a dielectric insulation layer, forming a structured mask layer on a side of the first electrically conductive layer that faces away from the dielectric insulation layer, forming at least one trench in the first electrically conductive layer, said at least one trench extending through the entire first electrically conductive layer to the dielectric insulation layer, forming a coating which covers at least the bottom and the side walls of the at least one trench, and removing the mask layer after the coating has been formed.

公开(公告)号：US11688712B2

公开(公告)日：2023-06-27

申请号：US16792682

申请日：2020-02-17

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld

IPC: H01L23/00 ,  H01L27/12

CPC classification number: H01L24/34 ,  H01L27/1248 ,  H01L2224/32013 ,  H01L2224/32054 ,  H01L2224/32055 ,  H01L2224/32056 ,  H01L2224/32059 ,  H01L2224/32113 ,  H01L2224/32258 ,  H01L2224/49175

Abstract: A semiconductor arrangement includes a semiconductor substrate having a dielectric insulation layer and at least a first metallization layer arranged on a first side of the dielectric insulation layer. The first metallization layer includes at least two sections, each section being separated from a neighboring section by a recess. A semiconductor body is arranged on one of the sections of the first metallization layer. At least one indentation is arranged between a first side of the semiconductor body and a closest edge of the respective section of the first metallization layer. A distance between the first side and the closest edge of the section of the first metallization layer is between 0.5 mm and 5 mm.

公开(公告)号：US11437311B2

公开(公告)日：2022-09-06

申请号：US16951556

申请日：2020-11-18

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L21/00 ,  H01L23/498 ,  H01L23/367 ,  H01L23/40 ,  H01L23/31 ,  H01L23/24 ,  H01L21/56 ,  H01L25/07 ,  H01L23/00

Abstract: A method for producing a power semiconductor module arrangement includes arranging two or more individual semiconductor devices on a base layer, each semiconductor device including a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame, arranging a frame on the base layer such that the frame surrounds the two or more individual semiconductor devices, and filling a first material into a capacity formed by the base layer and the frame, and hardening the first material to form a casting compound that at least partly fills the capacity, thereby at least partly encloses the two or more individual semiconductor devices.

公开(公告)号：US11081414B2

公开(公告)日：2021-08-03

申请号：US16260834

申请日：2019-01-29

Applicant: Infineon Technologies AG

Inventor： Alexander Roth ,  Olaf Hohlfeld

IPC: H01L23/24 ,  H01L23/053 ,  H01L21/56 ,  H01L23/29 ,  H01L21/54 ,  H01L23/00

Abstract: A power semiconductor module arrangement includes a substrate arranged in a housing. The substrate includes a first metallization layer arranged on a first side of a dielectric insulation layer and a second metallization layer arranged on a second side of the dielectric insulation layer. At least one semiconductor body is mounted on a first surface of the first metallization layer facing away from the dielectric insulation layer. A connecting element is arranged on and electrically connected to the first surface. A contact element is inserted into and electrically connected to the connecting element, and extends from the connecting element through an interior of the housing and through an opening in the cover of the housing to an outside of the housing in a direction perpendicular to the first surface. A hard encapsulation is arranged adjacent to the first metallization layer and at least partly fills the inside of the housing.