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公开(公告)号:US20160293581A1
公开(公告)日:2016-10-06
申请号:US15047980
申请日:2016-02-19
Applicant: MediaTek Inc.
Inventor: Tzu-Hung LIN , I-Hsuan PENG , Ching-Wen HSIAO
IPC: H01L25/065 , H01L23/31 , H01L23/498
CPC classification number: H01L25/0657 , H01L23/3157 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L25/105 , H01L25/16 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/24137 , H01L2224/24195 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2225/0651 , H01L2225/06527 , H01L2225/06544 , H01L2225/06555 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/1434 , H01L2924/1436 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19104 , H05K1/185 , H01L2924/00012 , H01L2924/00
Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace disposed at a first layer-level. A second conductive trace is disposed at a second layer-level. A first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, are disposed between the first conductive trace and the second conductive trace.
Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括包括第一半导体管芯的第一半导体封装。 第一再分配层(RDL)结构耦合到第一半导体管芯。 第一再分配层(RDL)结构包括设置在第一层级的第一导电迹线。 第二导电迹线设置在第二层级。 位于第一导电迹线和第二导电迹线之间的第一金属间电介质(IMD)层之外的第一金属间介电层(IMD)层和第二金属间介电层(IMD)层。
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公开(公告)号:US20160079220A1
公开(公告)日:2016-03-17
申请号:US14741796
申请日:2015-06-17
Applicant: MediaTek Inc.
Inventor: Tzu-Hung LIN , Ming-Tzong YANG
CPC classification number: H01L25/0657 , H01L23/3114 , H01L23/481 , H01L23/50 , H01L24/17 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L25/0655 , H01L25/10 , H01L25/105 , H01L25/18 , H01L2224/0237 , H01L2224/04105 , H01L2224/12105 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73209 , H01L2224/73265 , H01L2225/0651 , H01L2225/0652 , H01L2225/06541 , H01L2225/06562 , H01L2225/06572 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/1431 , H01L2924/1436 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/18162 , H05K1/112 , H05K1/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die having first pads thereon. First vias are disposed on the first semiconductor die, coupled to the first pads. A first dynamic random access memory (DRAM) die is mounted on the first semiconductor die, coupled to the first vias. A second semiconductor package is stacked on the first semiconductor package. The second semiconductor package includes a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface. A second dynamic random access memory (DRAM) die is mounted on the die-attach surface, coupled to the body through the bonding wires. The number of input/output (I/O) pins of first DRAM die is different from the number of input/output (I/O) pins of the second DRAM die.
Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括第一半导体封装。 第一半导体封装包括其上具有第一焊盘的第一半导体管芯。 第一通孔设置在第一半导体管芯上,耦合到第一焊盘。 第一动态随机存取存储器(DRAM)管芯安装在第一半导体管芯上,耦合到第一通孔。 第二半导体封装堆叠在第一半导体封装上。 第二半导体封装包括具有管芯附接表面和与管芯附接表面相对的凸起附着表面的主体。 第二动态随机存取存储器(DRAM)裸片安装在芯片附接表面上,通过接合线耦合到主体。 第一DRAM裸片的输入/输出(I / O)引脚的数量与第二DRAM裸片的输入/输出(I / O)引脚的数量不同。
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公开(公告)号:US20160079205A1
公开(公告)日:2016-03-17
申请号:US14932147
申请日:2015-11-04
Applicant: MediaTek Inc.
Inventor: Tzu-Hung LIN , I-Hsuan PENG , Ching-Wen HSIAO
IPC: H01L25/065 , H01L21/56 , H01L21/48 , H01L23/498 , H01L23/12
Abstract: The invention provides a semiconductor package, a semiconductor package assembly and a method for fabricating a semiconductor package. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die having first pads thereon. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. Conductive pillar structures are disposed on a surface of the first RDL structure away from the first semiconductor die, wherein the conductive pillar structures are coupled to the first RDL structure.
Abstract translation: 本发明提供半导体封装,半导体封装组件和用于制造半导体封装的方法。 半导体封装组件包括第一半导体封装。 第一半导体封装包括其上具有第一焊盘的第一半导体管芯。 第一再分配层(RDL)结构耦合到第一半导体管芯。 导电柱结构设置在远离第一半导体管芯的第一RDL结构的表面上,其中导电柱结构耦合到第一RDL结构。
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公开(公告)号:US20150357291A1
公开(公告)日:2015-12-10
申请号:US14826471
申请日:2015-08-14
Applicant: MediaTek Inc.
Inventor: Tzu-Hung LIN , Ching-Liou HUANG , Thomas Matthew GREGORICH
IPC: H01L23/00 , H01L23/31 , H01L23/498
CPC classification number: H01L24/17 , H01L21/563 , H01L23/3114 , H01L23/3142 , H01L23/49838 , H01L23/49894 , H01L23/50 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/32 , H01L2224/131 , H01L2224/16225 , H01L2224/16238 , H01L2224/26175 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/81193 , H01L2224/81815 , H01L2224/83102 , H01L2224/83855 , H01L2924/181 , H01L2924/1811 , H01L2924/183 , H01L2924/35 , H01L2924/00014 , H01L2924/014 , H01L2924/00
Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, a molding compound is provided that is formed over the substrate and covers the first conductive trace and the semiconductor die.
Abstract translation: 本发明提供一种半导体封装。 半导体封装包括衬底。 第一导电迹线设置在衬底上。 布置在基板上的第一导电迹线。 半导体管芯设置在第一导电迹线上。 还包括延伸穿过半导体管芯的边缘的阻焊层。 最后,提供了形成在衬底上并覆盖第一导电迹线和半导体晶粒的模塑料。
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公开(公告)号:US20150206855A1
公开(公告)日:2015-07-23
申请号:US14323107
申请日:2014-07-03
Applicant: MediaTek Inc.
Inventor: Tzu-Hung LIN
IPC: H01L25/065 , H01L23/00 , H01L23/48
CPC classification number: H01L25/0657 , H01L23/3128 , H01L23/481 , H01L23/5286 , H01L24/17 , H01L25/0655 , H01L2224/13024 , H01L2224/13025 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/181 , H01L2924/00
Abstract: The invention provides a semiconductor package. The semiconductor package includes a first semiconductor die having pads thereon. A first via and a second via are respectively disposed on the first semiconductor die. The first via connects to at least two of the pads of the first semiconductor die.
Abstract translation: 本发明提供一种半导体封装。 半导体封装包括其上具有焊盘的第一半导体管芯。 第一通孔和第二通孔分别设置在第一半导体管芯上。 第一通孔连接到第一半导体管芯的至少两个焊盘。
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公开(公告)号:US20130256878A1
公开(公告)日:2013-10-03
申请号:US13835701
申请日:2013-03-15
Applicant: MEDIATEK INC.
Inventor: Wen-Sung HSU , Tzu-Hung LIN , Ta-Jen YU
IPC: H01L23/498
CPC classification number: H01L23/49811 , H01L21/563 , H01L23/3142 , H01L23/3171 , H01L23/3178 , H01L23/3192 , H01L23/49838 , H01L24/05 , H01L24/08 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/26 , H01L24/32 , H01L24/73 , H01L2224/02331 , H01L2224/0401 , H01L2224/05012 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05552 , H01L2224/05569 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/13012 , H01L2224/13015 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/26175 , H01L2224/2919 , H01L2224/73204 , H01L2224/81385 , H01L2924/00014 , H01L2924/181 , H01L2924/014 , H01L2924/00012 , H01L2924/00
Abstract: The invention provides a semiconductor package. The semiconductor package includes a semiconductor package includes a substrate having a die attach surface. A die is mounted on die attach surface of the substrate via a conductive pillar bump. The die comprises a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has a first edge and a second edge substantially vertical to the first edge, wherein the length of the first edge is different from that of the second edge from a plan view.
Abstract translation: 本发明提供一种半导体封装。 半导体封装包括半导体封装,其包括具有管芯附接表面的衬底。 模具通过导电柱凸块安装在基板的芯片附着表面上。 芯片包括电耦合到导电柱凸起的金属焊盘,其中金属焊盘具有基本上垂直于第一边缘的第一边缘和第二边缘,其中第一边缘的长度与第二边缘的长度不同于 平面图。
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公开(公告)号:US20240274518A1
公开(公告)日:2024-08-15
申请号:US18645786
申请日:2024-04-25
Applicant: MEDIATEK INC.
Inventor: Tzu-Hung LIN , Yuan-Chin LIU
IPC: H01L23/498 , H01L23/00 , H01L23/31 , H01L25/065
CPC classification number: H01L23/49816 , H01L23/3192 , H01L24/13 , H01L24/45 , H01L24/73 , H01L25/0655
Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first substrate having a first wiring structure; and a second substrate having a second wiring structure, wherein the first substrate and the second substrate are arranged side-by-side, and the first substrate and the second substrate are surrounded and separated by a molding material. The semiconductor package structure also includes a redistribution layer disposed over the first substrate and the second substrate, wherein the redistribution layer is electrically coupled to the first wiring structure and the second wiring structure; and a frame surrounding the first substrate and the second substrate.
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公开(公告)号:US20230056550A1
公开(公告)日:2023-02-23
申请号:US18046218
申请日:2022-10-13
Applicant: MEDIATEK INC.
Inventor: Yen-Yao CHI , Nai-Wei LIU , Tzu-Hung LIN
Abstract: An electronic device that has an antenna device that includes a conductive pattern layer comprising a first antenna element, the conductive pattern layer formed in an insulating substrate and adjacent to a first surface of the insulating substrate, and a second antenna element formed on a second surface of the insulating substrate opposite the first surface. The electronic device further has a semiconductor package that includes a redistribution layer (RDL) structure bonded and electrically connected to the conductive pattern layer, a first electronic component electrically connected to the RDL structure, and an encapsulating layer formed on the RDL structure and surrounding the first electronic component.
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公开(公告)号:US20220336374A1
公开(公告)日:2022-10-20
申请号:US17810625
申请日:2022-07-04
Applicant: MEDIATEK INC.
Inventor: Tzu-Hung LIN , Chia-Cheng CHANG , I-Hsuan PENG , Nai-Wei LIU
IPC: H01L23/00 , H01L23/498 , H01L23/31 , H01L25/065 , H01L23/043 , H01L23/13 , H01L23/538
Abstract: A semiconductor package structure includes a substrate having a wiring structure. A first semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure. A second semiconductor die is disposed over the substrate and is electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged side-by-side. A hole is formed on a surface of the substrate, wherein the hole is located within projection of the first semiconductor die or the second semiconductor die on the substrate. Further, a molding material, surrounding the first semiconductor die and the second semiconductor die, and surfaces of the first semiconductor die and the second semiconductor die facing away from the substrate, are exposed by the molding material.
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公开(公告)号:US20220020726A1
公开(公告)日:2022-01-20
申请号:US17488921
申请日:2021-09-29
Applicant: MEDIATEK INC.
Inventor: Chia-Cheng CHANG , Tzu-Hung LIN , I-Hsuan PENG , Yi-Jou LIN
IPC: H01L25/065 , H01L23/538 , H01L23/31 , H01L23/498
Abstract: A semiconductor package structure includes a substrate having a substrate having a first surface and second surface opposite thereto, wherein the substrate comprises a wiring structure. The structure also has a first semiconductor die disposed on the first surface of the substrate and electrically coupled to the wiring structure, and a second semiconductor die disposed on the first surface and electrically coupled to the wiring structure, wherein the first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. A molding material surrounds the first semiconductor die and the second semiconductor die, wherein the first semiconductor die is separated from the second semiconductor die by the molding material. Finally, an annular frame mounted on the first surface of the substrate, wherein the annular frame surrounds the first semiconductor die and the second semiconductor die.
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