公开(公告)号：US10198315B2

公开(公告)日：2019-02-05

申请号：US15056070

申请日：2016-02-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Eran Sharon ,  Idan Alrod

IPC: G06F11/10 ,  G11C29/04 ,  H03M13/09 ,  G11C29/52 ,  H03M13/29

Abstract: A non-volatile storage system is provided that includes a mechanism to restore data that has been corrupted beyond the limits of traditional error correction. The system creates first level parity information for each subset of data to form multiple sets of programmable data, with each set of programmable data including a subset of data and corresponding first level parity. Separate second level parity is created for each set of programmable data. The system creates combined second level parity information based on a function of separate second level parity information for the multiple sets of programmable data. If a set of programmable data is found to be corrupt, the corrupt subset of data is recovered using the corrupt subset of data read from the non-volatile storage system, the corresponding first level parity read from the non-volatile storage system and the combined second level parity information.

公开(公告)号：US20180287632A1

公开(公告)日：2018-10-04

申请号：US15475666

申请日：2017-03-31

Applicant: SanDisk Technologies LLC

Inventor： Rami Rom ,  ldan Goldenberg ,  Alexander Bazarsky ,  Eran Sharon ,  Ran Zamir ,  ldan Alrod ,  Stella Achtenberg

IPC: H03M13/11 ,  H03M13/00 ,  G06F3/06

CPC classification number: H03M13/11 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0688 ,  H03M13/1125 ,  H03M13/6566

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

公开(公告)号：US20180203762A1

公开(公告)日：2018-07-19

申请号：US15921165

申请日：2018-03-14

Applicant: SanDisk Technologies LLC

Inventor： Idan Alrod ,  Eran Sharon ,  Alon Eyal ,  Liang Pang ,  Evgeny Mekhanik

IPC: G06F11/10 ,  G11C29/52 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08

CPC classification number: G06F11/1068 ,  G06F11/08 ,  G06F11/10 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C29/52 ,  G11C2207/2281

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.

公开(公告)号：US09947399B2

公开(公告)日：2018-04-17

申请号：US14669731

申请日：2015-03-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ariel Navon ,  Idan Alrod ,  Eran Sharon ,  Idan Goldenberg ,  Didi Gur

IPC: G06F11/10 ,  G11C13/00 ,  G11C29/52

CPC classification number: G11C13/0069 ,  G06F11/1048 ,  G06F11/1056 ,  G06F11/1068 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0097 ,  G11C29/52 ,  G11C2013/0076 ,  G11C2013/0085

Abstract: Data is initially programmed in a portion of ReRAM in parallel. Subsequently, one or more ReRAM cells in the portion are determined to contain first data that is to be modified while remaining ReRAM cells in the portion contain second data that is not to be modified. First conditions are applied to the one or more ReRAM cells thereby modifying the first data, while second conditions are applied to the remaining ReRAM cells, the second conditions maintaining the second data in the remaining ReRAM cells without significant change.

公开(公告)号：US09946468B2

公开(公告)日：2018-04-17

申请号：US15459578

申请日：2017-03-15

Applicant: SanDisk Technologies LLC

Inventor： Kevin Michael Conley ,  Raul-Adrian Cernea ,  Eran Sharon ,  Idan Alrod

IPC: G11C16/26 ,  G06F3/06 ,  G11C11/56 ,  G11C16/08 ,  G11C16/04 ,  G11C16/34 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1012 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/107 ,  G11C16/3459 ,  G11C29/52

Abstract: A non-volatile memory system including multi-level storage optimized for ramp sensing and soft decoding is provided. Sensing is performed at a higher bit resolution than an original user data encoding to improve the accuracy of reading state information from non-volatile storage elements. Higher resolution state information is used for decoding the original user data to improve read performance through improved error handling. Ramp sensing is utilized to determine state information by applying a continuous input scanning sense voltage that spans a range of read compare points. Full sequence programming is enabled as is interleaved coding of the user data over all of the data bit sets associated with the storage elements.

公开(公告)号：US11488682B2

公开(公告)日：2022-11-01

申请号：US16911333

申请日：2020-06-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tomer Eliash ,  Alexander Bazarsky ,  Eran Sharon

IPC: G11C29/14 ,  G11C29/44 ,  G11C29/42 ,  G11C29/46 ,  G11C16/26 ,  G11C16/10 ,  G11C29/12

Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die based on one or more operational parameters. The control die is configured to calibrate the one or more operational parameters for the memory die. The control die is also configured to perform testing of the memory die using the calibrated one or more operational parameters.

公开(公告)号：US20210407613A1

公开(公告)日：2021-12-30

申请号：US16911333

申请日：2020-06-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tomer Eliash ,  Alexander Bazarsky ,  Eran Sharon

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/46 ,  G11C29/14 ,  G11C16/10 ,  G11C16/26

Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die based on one or more operational parameters. The control die is configured to calibrate the one or more operational parameters for the memory die. The control die is also configured to perform testing of the memory die using the calibrated one or more operational parameters.

公开(公告)号：US10459787B2

公开(公告)日：2019-10-29

申请号：US15709769

申请日：2017-09-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Damian Yurzola ,  Eran Sharon ,  Idan Alrod ,  Michael Altshuler ,  Madhuri Kotagiri ,  Rajeev Nagabhirava

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52

Abstract: In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns.

公开(公告)号：US10355712B2

公开(公告)日：2019-07-16

申请号：US15475602

申请日：2017-03-31

Applicant: SanDisk Technologies LLC

Inventor： Rami Rom ,  Idan Goldenberg ,  Alexander Bazarsky ,  Eran Sharon ,  Ran Zamir ,  Idan Alrod ,  Stella Achtenberg

IPC: H03M13/11 ,  G06F11/10 ,  G06F3/06 ,  H03M13/00 ,  H03M13/37

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

公开(公告)号：US10075190B2

公开(公告)日：2018-09-11

申请号：US14924627

申请日：2015-10-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Stella Achtenberg ,  Eran Sharon ,  Ran Zamir

IPC: H03M13/00 ,  H03M13/37 ,  G06F11/10 ,  G11C29/52 ,  H03M13/45 ,  H03M13/11 ,  H03M13/15 ,  H03M13/29

CPC classification number: H03M13/3746 ,  G06F11/10 ,  G06F11/1072 ,  G11C29/52 ,  H03M13/1108 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116 ,  H03M13/1171 ,  H03M13/1191 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2957 ,  H03M13/3707 ,  H03M13/45

Abstract: A decoder includes a processor and a scheduler coupled to the processor. The processor is configured to process a set of nodes related to a representation of a codeword during a first decode iteration. The nodes are processed in a first order. The scheduler is configured to generate a schedule that indicates a second order of the set of nodes. The second order is different from the first order.