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    Nano-Enabled Memory Devices and Anisotropic Charge Carrying Arrays
    45.
    发明申请
    Nano-Enabled Memory Devices and Anisotropic Charge Carrying Arrays 有权
    具有纳米功能的存储器件和各向异性电荷携带阵列

    公开(公告)号：US20070187768A1

    公开(公告)日：2007-08-16

    申请号：US11695728

    申请日：2007-04-03

    申请人： Xiangfeng Duan ,  Calvin Chow ,  David Heald ,  Chunming Niu ,  J. Parce ,  David Stumbo

    发明人： Xiangfeng Duan ,  Calvin Chow ,  David Heald ,  Chunming Niu ,  J. Parce ,  David Stumbo

    IPC分类号： H01L29/94

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  G03G5/00 ,  G03G5/02 ,  G03G5/04 ,  G03G5/043 ,  G03G5/08 ,  G03G5/082 ,  G03G5/08214 ,  G11C11/56 ,  G11C13/02 ,  G11C13/025 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2216/08 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/7887 ,  Y10S977/774 ,  Y10S977/785 ,  Y10S977/936

    摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.

    摘要翻译： 描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。 在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。 纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米的群体包括金属量子点。 隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。 在纳米元件的薄膜上形成栅极接触。 纳米元件允许减少横向电荷转移。 存储器件可以是单个或多个存储器件。 在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了一种用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个 与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。

    APPLICATIONS OF NANO-ENABLED LARGE AREA MACROELECTRONIC SUBSTRATES INCORPORATING NANOWIRES AND NANOWIRE COMPOSITES
    46.
    发明申请
    APPLICATIONS OF NANO-ENABLED LARGE AREA MACROELECTRONIC SUBSTRATES INCORPORATING NANOWIRES AND NANOWIRE COMPOSITES 有权
    纳米复合纳米粒子和纳米复合材料纳米大面积微电子基板的应用

    公开(公告)号：US20060169788A1

    公开(公告)日：2006-08-03

    申请号：US11226187

    申请日：2005-09-14

    申请人： Stephen Empedocles ,  David Stumbo ,  Chunming Niu ,  Xiangfeng Duan

    发明人： Stephen Empedocles ,  David Stumbo ,  Chunming Niu ,  Xiangfeng Duan

    IPC分类号： G06K19/06

    CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C13/02 ,  G11C2213/16 ,  G11C2213/17 ,  G11C2213/18 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

    摘要： Macroelectronic substrate materials incorporating nanowires are described. These are used to provide underlying electronic elements (e.g., transistors and the like) for a variety of different applications. Methods for making the macroelectronic substrate materials are disclosed. One application is for transmission an reception of RF signals in small, lightweight sensors. Such sensors can be configured in a distributed sensor network to provide security monitoring. Furthermore, a method and apparatus for a radio frequency identification (RFID) tag is described. The RFID tag includes an antenna and a beam-steering array. The beam-steering array includes a plurality of tunable elements. A method and apparatus for an acoustic cancellation device and for an adjustable phase shifter that are enabled by nanowires are also described.

    摘要翻译： 描述了纳入纳米线的宏电子衬底材料。 这些用于为各种不同的应用提供底层电子元件（例如，晶体管等）。 公开了制造宏电子衬底材料的方法。 一个应用是在小型轻型传感器中传输RF信号的接收。 这样的传感器可以配置在分布式传感器网络中，以提供安全监控。 此外，描述了用于射频识别（RFID）标签的方法和装置。 RFID标签包括天线和波束导向阵列。 光束转向阵列包括多个可调谐元件。 还描述了用于通过纳米线实现的声消除装置和可调移相器的方法和装置。

    Gate electrode for a nonvolatile memory cell
    50.
    发明授权
    Gate electrode for a nonvolatile memory cell 有权
    用于非易失性存储单元的栅电极

    公开(公告)号：US08030161B2

    公开(公告)日：2011-10-04

    申请号：US12121591

    申请日：2008-05-15

    申请人： Xiangfeng Duan ,  Jian Chen ,  J. Wallace Parce ,  Francisco A. Leon

    发明人： Xiangfeng Duan ,  Jian Chen ,  J. Wallace Parce ,  Francisco A. Leon

    IPC分类号： H01L21/336 ,  H01L29/788

    CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/7883 ,  H01L29/7885

    摘要： A nonvolatile memory cell includes a substrate comprising a source, drain, and channel between the source and the drain. A tunnel dielectric layer overlies the channel, and a localized charge storage layer is disposed between the tunnel dielectric layer and a control dielectric layer. A gate electrode has a first surface adjacent to the control dielectric layer, and the first surface includes a midsection and two edge portions. According to one embodiment, the midsection defines a plane, and at least one edge portion extends away from the plane. Preferably, the edge portion extending away from the plane converges toward an opposing second surface of the gate electrode. According to another embodiment, the gate electrode of the nonvolatile memory cell includes a first sublayer and a second sublayer of a different width on the first sublayer.

    摘要翻译： 非易失性存储单元包括在源极和漏极之间包括源极，漏极和沟道的衬底。 隧道介电层覆盖在沟道上，并且局部电荷存储层设置在隧道介电层和控制电介质层之间。 栅电极具有与控制电介质层相邻的第一表面，并且第一表面包括中部和两个边缘部分。 根据一个实施例，中段限定一个平面，并且至少一个边缘部分远离平面延伸。 优选地，远离平面延伸的边缘部分朝向栅电极的相对的第二表面会聚。 根据另一实施例，非易失性存储单元的栅极包括第一子层和第一子层上具有不同宽度的第二子层。