Abstract:
A method or an apparatus for aligning a plurality of structures can include applying a first force in a first plane to a first structure. The method can also include constraining in the first plane the first structure with respect to a second structure such that the first structure is in a position with respect to the second structure that aligns first features on the first structure with second features on the second structures. The second feature can be in a second plane that is generally parallel to the first plane. The first and second structures can be first and second electronic components, which can be components of a probe card assembly.
Abstract:
A solar panel can include a substrate with layers of droplets of different materials disposed on a surface of the substrate. An outer layer can be disposed away from the surface and can comprise a face of the solar panel. The layers can comprise a cathode electrode and an anode electrode disposed between the outer layer and the surface of the substrate. The layers can further comprise a P region and an N region. The P region can be disposed at least partially around the anode electrode. The N region can be disposed at least partially around the P region and at least partially around the cathode electrode. The P region and the N region can comprise droplets of a P material comprising P-doped semiconductor particles and an N material comprising N-doped semiconductor particles respectively.
Abstract:
Embodiments of microspring arrays and methods for fabricating and using same are provided herein. In some embodiments, a microspring array may include at least two lithographically formed resilient contact elements, each resilient contact element having a beam and a tip for contacting a device to be tested, wherein the beams extend in substantially the same direction relative to a first end of the beams, and wherein the ends of the at least two beams are separated by a distance defining a central region and wherein the respective tips of the at least two beams extend away from the beams in a non-zero, non-perpendicular direction into the central region.
Abstract:
A stiffener structure, a wiring substrate, and a frame having a major surface disposed in a stack can be part of a probe card assembly. The wiring substrate can be disposed between the frame and the stiffener structure, and probe substrates can be coupled to the frame by one or more non-adjustably fixed coupling mechanisms. Each of the probe substrates can have probes that are electrically connected through the probe card assembly to an electrical interface on the wiring substrate to a test controller. The non-adjustably fixed coupling mechanisms can be simultaneously stiff in a first direction perpendicular to the major surface and flexible in a second direction generally parallel to the major surface.
Abstract:
A probe card assembly, according to some embodiments of the invention, can comprise a tester interface configured to make electrical connections with a test controller, a plurality of electrically conductive probes disposed to contact terminals of an electronic device to be tested, and a plurality of electrically conductive data paths connecting the tester interface and the probes. At least one of the data paths can comprise an air bridge structure trace comprising an electrically conductive trace spaced away from an electrically conductive plate by a plurality of pylons.
Abstract:
An interconnection apparatus and a method of forming an interconnection apparatus. Contact structures are attached to or formed on a first substrate. The first substrate is attached to a second substrate, which is larger than the first substrate. Multiple such first substrates may be attached to the second substrate in order to create an array of contact structures. Each contact structure may be elongate and resilient and may comprise a core that is over coated with a material that imparts desired structural properties to the contact structure.
Abstract:
Microelectronic contact structures (260, 360, 460) are lithographically defined and fabricated by applying a masking layer (220, 320, 420) on a surface of a substrate (202, 302, 402) such as an electronic component, creating an opening (222, 322, 422) in the masking layer, depositing a conductive trace of a seed layer (250, 350, 450) onto the masking layer and into the openings, and building up a mass of conductive material on the conductive trace. The sidewalls of the opening can be sloped (tapered). The conductive trace can be patterned by depositing material through a stencil or shadow mask (240, 340, 440). A protruding feature (230, 430) may be disposed on the masking layer so that a tip end (264, 364, 464) of the contact structure acquires a topography. All of these elements can be constructed as a group to form a plurality of precisely positioned resilient contact structures.
Abstract:
A method of making a tooling die can include depositing a plurality of layers onto a substrate using a printing process. Selected portions of the plurality of layers can be removed to expose a surface defining a desired shape of the tooling die. An electrically conductive material can be deposited to form a seed layer, and a structural material can be electrodeposited onto the seed layer to form the tooling die. The tooling die can be used to form contact structures on an electronic component.
Abstract:
Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. A significant reduction in interconnect count and consequent simplification of the interconnection substrate is realized because the ASICs are capable of receiving a plurality of signals for testing the DUTs over relatively few signal lines from a host controller and promulgating these signals over the relatively many interconnections between the ASICs and the DUTs. The ASICs can also generate at least a portion of these signals in response to control signals from the host controller. Physical alignment techniques are also described. Micromachined indentations on the front surface of the ASICs ensure capturing free ends of the spring contact elements. Micromachined features on the back surface of the ASICs and the front surface of the interconnection substrate to which they are mounted facilitate precise alignment of a plurality of ASICs on the support substrate.
Abstract:
A thermal adjustment apparatus for adjusting one or more thermally induced movements of an electro-mechanical assembly includes: a compensating element expanding at a first rate different from a second rate at which the electro-mechanical assembly expands for generating a counteracting force in response to changes in temperature; and a coupling mechanism coupling the compensating element to the electro-mechanical assembly, and being adjustable to control an amount of the counteracting force applied to the electro-mechanical assembly as temperature changes.