公开(公告)号：US20120276401A1

公开(公告)日：2012-11-01

申请号：US13544247

申请日：2012-07-09

Applicant: Katsuyoshi NAKAYAMA

Inventor： Katsuyoshi NAKAYAMA

IPC: B32B3/24 ,  B05D5/12

CPC classification number: H05K3/246 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49866 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/281 ,  H05K2201/099 ,  H05K2201/10106 ,  Y10T428/12361 ,  H01L2924/00

Abstract: To provide a substrate for mounting an element having good sulfurization resistance. A substrate 1 for mounting an element, comprising a low temperature co-fired ceramic substrate 2, a thick film conductor layer 3 made of a metal composed mainly of silver, which is formed on the surface of the low temperature co-fired ceramic substrate 2, a covering 4 made of a low temperature co-fired ceramic, which covers the edge portion 31 of the thick film conductor layer 3 and which is bonded to the low temperature co-fired ceramic substrate 2 on the outer side of the edge portion 31, and a plated layer 5 made of an electrically conductive metal, which is formed on the surface of the thick film conductor layer 3.

Abstract translation: 提供用于安装耐硫化性好的元件的基板。 用于安装元件的基板1，其包括低温共烧陶瓷基板2，由主要由银构成的金属制成的厚膜导体层3，其形成在低温共烧陶瓷基板2的表面上 ，由低温共烧陶瓷制成的覆盖物4，其覆盖厚膜导体层3的边缘部31，并且在边缘部31的外侧与低温共烧陶瓷基板2接合 以及形成在厚膜导体层3的表面上的由导电金属制成的镀层5。

公开(公告)号：US08283790B2

公开(公告)日：2012-10-09

申请号：US12691716

申请日：2010-01-21

Applicant: Wen-Chieh Tsou

Inventor： Wen-Chieh Tsou

IPC: H01L33/00 ,  H01L23/495 ,  H01L23/498

CPC classification number: H05K1/111 ,  H01L23/49555 ,  H01L24/48 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/3421 ,  H05K3/3452 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/099 ,  H05K2201/10106 ,  H05K2201/10651 ,  H05K2201/10689 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic device includes a carrier, a surface mounting device, and solders. The carrier has a plurality of bonding pads, and at least one of the bonding pads has a notch, such that the bonding pad has a necking portion adjacent to the notch. The surface mounting device is disposed on the carrier. Besides, the surface mounting device has a plurality of leads, and each of the leads is connected to the necking portion of one of the bonding pads, respectively. The notch of each of the bonding pads is located under one of the leads. The solders connect the bonding pads and the leads.

Abstract translation: 电子设备包括载体，表面安装装置和焊料。 载体具有多个接合焊盘，并且至少一个接合焊盘具有凹口，使得焊盘具有与凹口相邻的颈缩部分。 表面安装装置设置在载体上。 此外，表面安装装置具有多个引线，并且每个引线分别连接到一个接合焊盘的颈缩部分。 每个接合焊盘的凹口位于一个引线下方。 焊料连接焊盘和引线。

公开(公告)号：US20120152600A1

公开(公告)日：2012-06-21

申请号：US13307499

申请日：2011-11-30

Applicant: Hiroyuki NISHIOKA ,  Ryojiro Tominaga ,  Tatsuya Imai

Inventor： Hiroyuki NISHIOKA ,  Ryojiro Tominaga ,  Tatsuya Imai

IPC: H05K1/02 ,  B05D5/12

CPC classification number: H05K3/4007 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/099 ,  H05K2203/0594

Abstract: A printed wiring board including an interlayer resin insulation layer, a pad formed on the interlayer resin insulation layer and for mounting an electronic component, a solder-resist layer formed on the interlayer resin insulation layer and the pad and having an opening portion over the pad, and a coating layer formed on the pad and exposed through the opening portion of the solder-resist layer. The solder-resist layer has a protruding portion protruding toward the inside of the opening portion in a bottom portion of the opening portion, and the protruding portion of the solder-resist layer has a flat surface in an end portion of the protruding portion.

Abstract translation: 一种印刷电路板，包括层间树脂绝缘层，形成在层间树脂绝缘层上并用于安装电子部件的焊盘，形成在层间树脂绝缘层和焊盘上的阻焊层，并且在焊盘上具有开口部分 以及形成在焊盘上并通过阻焊层的开口部露出的涂层。 阻焊层具有在开口部的底部朝向开口部的内侧突出的突出部，并且阻焊层的突出部在突出部的端部具有平坦的表面。

公开(公告)号：US08173910B2

公开(公告)日：2012-05-08

申请号：US12178973

申请日：2008-07-24

Applicant: Alan L. Barry

Inventor： Alan L. Barry

IPC: H05K1/11 ,  H05K1/18

CPC classification number: H05K3/3452 ,  H01L2224/16225 ,  H05K1/111 ,  H05K1/116 ,  H05K3/3436 ,  H05K3/42 ,  H05K2201/0949 ,  H05K2201/099

Abstract: A printed circuit board (PCB) ball grid array (BGA) system is provided. In one embodiment, the PCB BGA system includes a PCB, a PCB BGA pad formed on the PCB, a plated through-hole via disposed at least partially through the PCB proximate the PCB BGA pad, and a soldermask disposed over the PCB. The soldermask includes: (i) a BGA pad opening through which the PCB BGA pad is exposed, and (ii) a via opening through which a central portion of the plated through-hole via is exposed. The via opening has an inner diameter that is less than the outer diameter of the plated through-hole via.

Abstract translation: 提供印刷电路板（PCB）球栅阵列（BGA）系统。 在一个实施例中，PCB BGA系统包括印刷电路板，PCB上形成的PCB BGA焊盘，至少部分地通过PCB布置在PCB BGA焊盘附近的电镀通孔，以及设置在PCB上的焊接掩模。 焊接掩模包括：（i）BGA焊盘开口，PCB BGA焊盘穿过该BGA焊盘开口，以及（ii）暴露电镀通孔通孔的中心部分的通孔。 通孔开口具有小于电镀通孔通孔的外径的内径。

公开(公告)号：US20120032337A1

公开(公告)日：2012-02-09

申请号：US12852196

申请日：2010-08-06

Applicant: Chen-Fa Lu ,  Chen-Hua Yu ,  Chung-Shi Liu

Inventor： Chen-Fa Lu ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC: H01L23/498 ,  H01L21/50 ,  H05K1/18

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/099 ,  H05K2201/10674

Abstract: Apparatus and methods for providing a package substrate and assembly for a flip chip integrated circuit. A substrate is provided having a solder mask layer, openings in the solder mask layer for conductive bump pads, and openings in the solder mask layer between the conductive bump pads exposing a dielectric layer underneath the solder mask layer. A flip chip integrated circuit is attached to the substrate using a thermal reflow to reflow conductive solder bumps on the integrated circuit to the conductive bump pads. An underfill material is dispensed beneath the integrated circuit and physically contacting the dielectric layer of the substrate. In additional embodiments, one or more integrated circuits are flip chip mounted to the substrate. The resulting assembly has improved thermal characteristics over the assemblies of the prior art.

Abstract translation: 用于提供用于倒装芯片集成电路的封装衬底和组件的装置和方法。 提供了一种衬底，其具有焊接掩模层，用于导电凸块焊盘的焊料掩模层中的开口，以及在焊料掩模层之间的焊料掩模层中的暴露出阻焊掩模层下面的介电层的开口。 使用热回流将倒装芯片集成电路附接到基板，以将集成电路上的导电焊料凸起回流到导电凸块焊盘。 底部填充材料被分配在集成电路下面并物理接触衬底的电介质层。 在另外的实施例中，将一个或多个集成电路倒装芯片安装到基板。 所得组件相对于现有技术的组件具有改善的热特性。

公开(公告)号：US08026616B2

公开(公告)日：2011-09-27

申请号：US12352056

申请日：2009-01-12

Applicant: Soon-yong Hur ,  Mo-rae Kim ,  Hyeong-seob Kim

Inventor： Soon-yong Hur ,  Mo-rae Kim ,  Hyeong-seob Kim

IPC: H01L23/52 ,  H01L23/48

CPC classification number: H05K3/3452 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/111 ,  H05K2201/09381 ,  H05K2201/0989 ,  H05K2201/099 ,  Y02P70/611 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A printed circuit board providing high reliability using a packaging of high capacity semiconductor chip, a semiconductor package, and a card and a system using the semiconductor package. The semiconductor package includes a substrate having a first surface and a second surface, a semiconductor chip mounted on the first surface of the substrate, at least one land disposed on the second surface of the substrate, and whose circumference includes a plurality of first group arcs, a mask layer covering the second surface of the substrate and including at least one opening that exposes the at least one land, and at least one external terminal disposed on the at least one land, wherein a portion of the at least one land is covered by the mask layer, and a sidewall of another portion of the at least one land is exposed by the at least one opening, and the circumference of the at least one opening includes a plurality of second group arcs, and a radius of the outermost arc from among the plurality of first group arcs is equal to a radius of the outermost arc from among the plurality of second group arcs.

Abstract translation: 一种印刷电路板，其使用大容量半导体芯片，半导体封装和卡的封装以及使用半导体封装的系统提供高可靠性。 半导体封装包括具有第一表面和第二表面的衬底，安装在衬底的第一表面上的半导体芯片，设置在衬底的第二表面上的至少一个焊盘，并且其周边包括多个第一组弧 覆盖基板的第二表面并包括暴露至少一个焊盘的至少一个开口的掩模层和设置在至少一个焊盘上的至少一个外部端子，其中所述至少一个焊盘的一部分被覆盖 并且所述至少一个平台的另一部分的侧壁被所述至少一个开口暴露，并且所述至少一个开口的圆周包括多个第二组弧，并且所述最外弧的半径 多个第一组弧之间的距离等于多个第二组弧之中的最外弧的半径。

公开(公告)号：US08017875B2

公开(公告)日：2011-09-13

申请号：US11476559

申请日：2006-06-29

Applicant: Yoichiro Kawamura ,  Shigeki Sawa ,  Katsuhiko Tanno ,  Hironori Tanaka ,  Naoaki Fujii

Inventor： Yoichiro Kawamura ,  Shigeki Sawa ,  Katsuhiko Tanno ,  Hironori Tanaka ,  Naoaki Fujii

IPC: H05K1/16

CPC classification number: H05K3/3478 ,  B23K3/0623 ,  B23K2101/42 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/544 ,  H01L24/81 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/3452 ,  H05K2201/0191 ,  H05K2201/099 ,  H05K2203/041 ,  H05K2203/0557 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed wiring board includes a wiring substrate, one or more conductor circuits provided on the wiring substrate, a solder resist layer provided on a surface of the wiring substrate and having multiple openings, the openings exposing multiple parts of the conductor circuits forming multiple conductor pads for mounting electronic parts, and multiple solder bumps formed on the conductor pads, respectively. The conductor pads are aligned at a pitch of about 200 μm or less, and a ratio W/D of a diameter W of the solder bumps to an opening diameter D of the openings formed in the solder resist layer is about 1.05 to about 1.7.

Abstract translation: 印刷电路板包括布线基板，设置在布线基板上的一个或多个导体电路，设置在布线基板的表面上并具有多个开口的阻焊层，所述开口暴露导体电路的多个部分，形成多个导体焊盘 用于安装电子部件，以及形成在导体焊盘上的多个焊料凸块。 导体焊盘以约200μm以下的间距排列，并且焊料凸块的直径W与形成在阻焊层中的开口的开口直径D的比率W / D为约1.05至约1.7。

公开(公告)号：US07998560B2

公开(公告)日：2011-08-16

申请号：US12266574

申请日：2008-11-07

Applicant: Yasutaka Sugimoto

Inventor： Yasutaka Sugimoto

IPC: B32B9/00

CPC classification number: H05K1/111 ,  C03C14/004 ,  H05K1/0306 ,  H05K3/285 ,  H05K3/4614 ,  H05K3/4629 ,  H05K2201/017 ,  H05K2201/068 ,  H05K2201/09481 ,  H05K2201/099 ,  Y02P70/611 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A multilayer ceramic substrate includes an inner layer portion and surface portions that sandwich the inner layer portion in the stacking direction and have an increased transverse strength because of the surface layer portion having a thermal expansion coefficient less than that of the inner layer portion. At least one of the surface portions covers peripheries of main-surface conductive films arranged on a main surface of an inner portion so as to leave central portions of the main-surface conductive films exposed, so that the main-surface conductive films function as via conductors, thereby eliminating the need to provide a via conductor in the surface portions.

Abstract translation: 多层陶瓷基板包括内层部分和由于表面层部分的热膨胀系数小于内层部分的热膨胀系数而在层叠方向上夹着内层部分并具有增加的横向强度的表面部分。 表面部分中的至少一个覆盖布置在内部主表面上的主表面导电膜的周边，以使主表面导电膜的中心部分露出，使得主表面导电膜用作通孔 导体，从而不需要在表面部分中提供通孔导体。

公开(公告)号：US20110155443A1

公开(公告)日：2011-06-30

申请号：US12979474

申请日：2010-12-28

Applicant: Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Takuya HANDO ,  Tatsuya ITO ,  Satoshi HIRANO ,  Atsuhiko SUGIMOTO

Inventor： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Takuya HANDO ,  Tatsuya ITO ,  Satoshi HIRANO ,  Atsuhiko SUGIMOTO

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K1/0298 ,  H01L21/4846 ,  H01L23/49822 ,  H01L2224/16225 ,  H05K1/09 ,  H05K1/111 ,  H05K1/113 ,  H05K3/0055 ,  H05K3/3452 ,  H05K3/4682 ,  H05K2201/068 ,  H05K2201/094 ,  H05K2201/0989 ,  H05K2201/099

Abstract: In a build-up step, a plurality of resin insulation layers and a plurality of conductive layers are alternately laminated in multilayer arrangement on a metal foil separably laminated on a side of a base material, thereby forming a wiring laminate portion. In a drilling step, a plurality of openings are formed in an outermost resin insulation layer through laser drilling so as to expose connection terminals. Subsequently, in a desmear step, smears from inside the openings are removed. In a base-material removing step performed after the build-up step, the base material is removed and the metal foil is exposed.

Abstract translation: 在堆积步骤中，将多个树脂绝缘层和多个导电层以多层布置交替层叠在可分离地层叠在基材侧上的金属箔上，从而形成布线层压体部分。 在钻井工序中，通过激光钻孔在最外层的树脂绝缘层上形成多个开口，露出连接端子。 随后，在去污步骤中，去除开口内部的污迹。 在堆积步骤之后执行的基材除去步骤中，除去基材并暴露金属箔。

公开(公告)号：US20110100695A1

公开(公告)日：2011-05-05

申请号：US12646904

申请日：2009-12-23

Applicant: Hsien-Chieh Lin

Inventor： Hsien-Chieh Lin

IPC: H05K1/11

CPC classification number: H05K1/111 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/4644 ,  H05K2201/09745 ,  H05K2201/099 ,  Y02P70/611 ,  H01L2924/00

Abstract: Disclosed is a printed circuit board structure which is manufactured by providing a core board, forming an inner circuit layer on the core board surface, forming a bonding pad on the inner circuit, forming a ring-shaped anti-etching layer on the bonding pad, forming an anti-soldering insulation layer on the ring-shaped anti-etching layer and the bonding pad, and forming an opening to expose a part of the bonding pad, wherein the radius of the opening is shorter than the radius of the ring-shaped anti-etching layer, and the bonding pad surface is free of concave. The described structure may prevent the solder extending along the bottom void of the anti-soldering insulation layer to other regions.

Abstract translation: 公开了一种印刷电路板结构，其通过提供芯板来制造，在芯板表面上形成内部电路层，在内部电路上形成接合焊盘，在接合焊盘上形成环状抗蚀刻层， 在所述环形防蚀层和所述接合焊盘上形成防焊绝缘层，并且形成用于暴露所述接合焊盘的一部分的开口，其中所述开口的半径比所述环形防蚀层的半径小 抗蚀刻层，并且焊盘表面没有凹陷。 所描述的结构可以防止焊料沿着防焊绝缘层的底部空隙延伸到其它区域。