公开(公告)号：US12051749B2

公开(公告)日：2024-07-30

申请号：US17228550

申请日：2021-04-12

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jiamin Wang ,  Blanka Magyari-Kope ,  Ashwathi Iyer ,  Chris Liu

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786 ,  H10B51/30

CPC分类号： H01L29/78391 ,  H01L21/02565 ,  H01L29/40111 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H10B51/30

摘要： A semiconductor structure includes, from bottom to top or from top to bottom, a gate electrode, a ferroelectric dielectric layer, a metal-rich metal oxide layer, a dielectric metal nitride layer, and a metal oxide semiconductor layer. A ferroelectric field effect transistor may be provided by forming a source region and a drain region on the metal oxide semiconductor layer. The metal-rich metal oxide layer and the dielectric metal nitride layer homogenize and stabilize the interface between the ferroelectric dielectric layer and the metal oxide semiconductor layer, and reduce excess oxygen atoms at the interface, thereby improving switching characteristics of the ferroelectric field effect transistor.

公开(公告)号：US12051734B2

公开(公告)日：2024-07-30

申请号：US18076958

申请日：2022-12-07

申请人： Applied Materials, Inc.

发明人： Srinivas Gandikota ,  Steven C. H. Hung ,  Mandyam Sriram ,  Jacqueline S. Wrench ,  Yixiong Yang ,  Yong Yang

IPC分类号： H01L29/40 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L21/285

CPC分类号： H01L29/4966 ,  H01L29/401 ,  H01L29/517 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/28568 ,  H01L29/518

摘要： Metal gate stacks and integrated methods of forming metal gate stacks are disclosed. Some embodiments comprise NbN as a PMOS work function material at a thickness in a range of greater than or equal to 5 Å to less than or equal to 50 Å. The PMOS work function material comprising NbN has an effective work function of greater than or equal to 4.75 eV. Some embodiments comprise HfO2 as a high-κ metal oxide layer. Some embodiments provide improved PMOS bandedge performance evidenced by improved flatband voltage. Some embodiments exclude transition metal niobium nitride materials as work function materials.

公开(公告)号：US20240250151A1

公开(公告)日：2024-07-25

申请号：US18628112

申请日：2024-04-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Hao Chang ,  Lin-Yu Huang ,  Sheng-Tsung Wang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/6656 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/0653

摘要： Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.

公开(公告)号：US20240250150A1

公开(公告)日：2024-07-25

申请号：US18443994

申请日：2024-02-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sheng-Liang Pan ,  Chen Yung Tzu ,  Chung-Chieh Lee ,  Yung-Chang Hsu ,  Hung Chia-Yang ,  Po-Chuan Wang ,  Guan-Xuan Chen ,  Huan-Just Lin

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/6656 ,  H01L21/02126 ,  H01L21/0217 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

摘要： A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.

公开(公告)号：US20240250144A1

公开(公告)日：2024-07-25

申请号：US18585978

申请日：2024-02-23

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Byounghoon Lee ,  Jongho Park ,  Wandon Kim ,  Sangjin Hyun

IPC分类号： H01L29/49 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/3215 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L21/3115 ,  H01L21/3215

摘要： A semiconductor device includes a substrate having first and second active regions, first and second active patterns on the first and second active regions, first and second gate electrodes running across the first and second active patterns, and a high-k dielectric layer between the first active pattern and the first gate electrode and between the second active pattern and the second gate electrode. The first gate electrode includes a work function metal pattern and an electrode pattern. The second gate electrode includes a first work function metal pattern, a second work function metal pattern, and an electrode pattern. The first work function metal pattern contains the same impurity as that of the high-k dielectric layer. An impurity concentration of the first work function metal pattern of the second gate electrode is greater than that of the work function metal pattern of the first gate electrode.

公开(公告)号：US12046683B2

公开(公告)日：2024-07-23

申请号：US17861432

申请日：2022-07-11

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Yutaka Okazaki ,  Akihisa Shimomura ,  Naoto Yamade ,  Tomoya Takeshita ,  Tetsuhiro Tanaka

IPC分类号： H01L29/786 ,  H01L27/12 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/78696 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/7869

摘要： A transistor with favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a semiconductor, a first insulator in contact with the semiconductor, a first conductor in contact with the first insulator and overlapping with the semiconductor with the first insulator positioned between the semiconductor and the first conductor, and a second conductor and a third conductor, which are in contact with the semiconductor. One or more of the first to third conductors include a region containing tungsten and one or more elements selected from silicon, carbon, germanium, tin, aluminum, and nickel.

公开(公告)号：US12046632B2

公开(公告)日：2024-07-23

申请号：US18182893

申请日：2023-03-13

申请人： Samsung Electronics Co., Ltd.

发明人： Haejun Yu ,  Kyungin Choi ,  Seung Hun Lee

IPC分类号： H01L29/06 ,  B82Y10/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/0653 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/66553 ,  H01L27/092

摘要： A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, the channel pattern including semiconductor patterns stacked and spaced apart from each other, a gate electrode extending across the channel pattern, and inner spacers between the gate electrode and the source/drain pattern. The semiconductor patterns include stacked first and second semiconductor patterns. The gate electrode includes first and second portions, which are sequentially stacked between the substrate and the first and second semiconductor patterns, respectively. The inner spacers include first and second air gaps, between the first and second portions of the gate electrode and the source/drain pattern. The largest width of the first air gap is larger than that of the second air gap.

公开(公告)号：US12040383B2

公开(公告)日：2024-07-16

申请号：US17465762

申请日：2021-09-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Lin Lee ,  Choh Fei Yeap ,  Da-Wen Lin ,  Chih-Chieh Yeh

IPC分类号： H01L29/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/764 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/66742 ,  H01L21/0259 ,  H01L21/28123 ,  H01L21/764 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78621 ,  H01L29/78696

摘要： A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.

公开(公告)号：US12040375B2

公开(公告)日：2024-07-16

申请号：US17249918

申请日：2021-03-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Liang Cheng

IPC分类号： H01L29/66 ,  H01L21/3065 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/4933 ,  H01L21/3065 ,  H01L27/0688 ,  H01L29/0669 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/785 ,  H01L2029/7858

摘要： A semiconductor device includes a multi-silicide structure comprising at least two conformal silicide layers. The multi-silicide structure may include a first conformal silicide layer on a source/drain, a second conformal silicide layer on the first conformal silicide layer, and a capping layer over the second conformal silicide layer. The semiconductor device includes a contact structure on the multi-silicide structure. The semiconductor device includes a dielectric material around the contact structure. In some implementations, a controller may determine etch process parameters to be used by an etch tool to perform an iteration of an atomic layer etch (ALE) process on the semiconductor device.

公开(公告)号：US12040330B2

公开(公告)日：2024-07-16

申请号：US18139493

申请日：2023-04-26

申请人： InnoLux Corporation

发明人： Chandra Lius ,  Nai-Fang Hsu

IPC分类号： H01L33/36 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1368 ,  G06F3/041 ,  H01L27/12 ,  H01L29/24 ,  H01L29/423 ,  H01L29/786 ,  H10K59/131 ,  H10K59/40 ,  H01L29/49 ,  H10K59/121

CPC分类号： H01L27/1225 ,  G02F1/133345 ,  G02F1/13338 ,  G02F1/134309 ,  G02F1/1368 ,  G06F3/0412 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/78648 ,  H01L29/78675 ,  H01L29/7869 ,  H01L29/78696 ,  H10K59/131 ,  H10K59/40 ,  G02F1/133388 ,  G02F1/13685 ,  H01L29/4908 ,  H01L29/78672 ,  H10K59/1213

摘要： An electronic device includes: a first substrate; a silicon semiconductor layer disposed on the first substrate; a first oxide semiconductor layer and a second oxide semiconductor layer disposed on the first substrate; a first conductive component disposed on the first substrate and electrically connected to the silicon semiconductor layer; and a second conductive component disposed on the first conductive component and electrically connected to at least one of the first oxide semiconductor layer and the second oxide semiconductor layer, wherein the second conductive component is at least partially overlapped with the first oxide semiconductor layer and the first conductive component.