公开(公告)号：US20190112693A1

公开(公告)日：2019-04-18

申请号：US15553656

申请日：2016-02-24

Applicant: In-Young LEE

Inventor： In-Young LEE ,  Kang-Hyung KIM ,  Hyun-Seok JEON

IPC: C22C23/04 ,  C22C1/03

Abstract: Disclosed is a magnesium alloy that has high thermal conductivity and flame retardancy and facilitates plastic working, wherein magnesium is added with 0.5 to 5 wt % of zinc and 0.6 to 3.5 wt % of tin (Sn) as a high-melting-point oxide-film-forming element, with, as necessary, 1.5 wt % or less of at least one selected from among calcium (Ca), silicon (Si), manganese (Mn) and mischmetal, the total amount of alloy elements being 2.5 to 6.3 wt %. A method of manufacturing the same is also provided, including melting high-melting-point alloy elements in the form of a master alloy in a magnesium—zinc alloy melt, followed by casting, removing a chill from the cast material, diffusion annealing, and then molding through a tempering process such as rolling, extrusion or forging. This magnesium alloy is improved in ductility by the action of alloy elements for inhibiting the formation of plate-like precipitates in a magnesium matrix structure, can be extruded even at a pressure of 1,000 kgf/cm2 or less due to the increased plasticity thereof, and can exhibit thermal conductivity of 100 W/m·K or more and flame retardancy satisfying the requirements for aircraft materials and is thus suitable for use in fields requiring fire safety, thereby realizing wide application thereof as a heat sink or a structural material for portable appliances, vehicles and aircraft components and contributing to weight reduction.

公开(公告)号：US08362621B2

公开(公告)日：2013-01-29

申请号：US12393109

申请日：2009-02-26

Applicant: Ho Jin Lee ,  Dong Hyeon Jang ,  Nam Seog Kim ,  In Young Lee ,  Ha Young Yim

Inventor： Ho Jin Lee ,  Dong Hyeon Jang ,  Nam Seog Kim ,  In Young Lee ,  Ha Young Yim

IPC: H01L23/522 ,  H01L25/11

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01055 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941

Abstract: A microelectronic structure includes a conductive pad on a substrate. The conductive pad includes first and second openings extending therethrough. A first conductive via on the conductive pad extends through the first opening in the conductive pad into the substrate. A second conductive via on the conductive pad adjacent the first conductive via extends through the second opening in the conductive pad into the substrate. At least one of the conductive vias may be electrically isolated from the conductive pad. Related devices and fabrication methods are also discussed.

Abstract translation: 微电子结构包括在衬底上的导电焊盘。 导电垫包括延伸穿过其中的第一和第二开口。 导电焊盘上的第一导电通孔延伸穿过导电焊盘中的第一开口进入衬底。 邻近第一导电通孔的导电焊盘上的第二导电通孔延伸穿过导电焊盘中的第二开口进入衬底。 导电通孔中的至少一个可以与导电焊盘电绝缘。 还讨论了相关设备和制造方法。

公开(公告)号：US08119448B2

公开(公告)日：2012-02-21

申请号：US12817304

申请日：2010-06-17

Applicant: Son-Kwan Hwang ,  In-Young Lee ,  Ho-Jin Lee ,  Dong-Hyeon Jang

Inventor： Son-Kwan Hwang ,  In-Young Lee ,  Ho-Jin Lee ,  Dong-Hyeon Jang

IPC: H01L21/00

CPC classification number: H01L24/11 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/9201 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10329 ,  H01L2224/05552

Abstract: A semiconductor chip comprises a substrate including a front surface and a rear surface, the substrate having a first via hole formed in the front surface and a second via hole formed in the rear surface, a first conductive plug formed on the substrate, the first conductive plug including a first portion formed in the first via hole and a second portion protruding from the front surface of the substrate, and a second conductive plug formed on the first conductive plug, the second conductive plug having a smaller cross-sectional area than the first conductive plug.

Abstract translation: 一种半导体芯片，包括：具有前表面和后表面的基板，所述基板具有形成在所述前表面上的第一通孔和形成在所述后表面中的第二通孔，形成在所述基板上的第一导电塞，所述第一导电 所述插头包括形成在所述第一通孔中的第一部分和从所述基板的前表面突出的第二部分，以及形成在所述第一导电插塞上的第二导电插塞，所述第二导电插塞具有比所述第一通孔更小的横截面积 导电插头

公开(公告)号：US20110086849A1

公开(公告)日：2011-04-14

申请号：US12934638

申请日：2009-04-16

Applicant: Ji Duck Kim ,  Hong-Chul Yoon ,  Seong Hee Cho ,  Inwoo Kim ,  Min Jae Cho ,  IN Young Lee ,  Hyae Jung Hyun ,  Eunkyung Park

Inventor： Ji Duck Kim ,  Hong-Chul Yoon ,  Seong Hee Cho ,  Inwoo Kim ,  Min Jae Cho ,  IN Young Lee ,  Hyae Jung Hyun ,  Eunkyung Park

IPC: A61K31/538 ,  C07D498/04 ,  A61P25/00 ,  A61P13/10 ,  A61P3/04 ,  A61P11/00 ,  A61P27/06 ,  A61P17/06 ,  A61P29/00 ,  A61P1/04

CPC classification number: C07D413/14 ,  C07D413/04

Abstract: The present invention relates to a novel benzoxazine benzimidazole derivative of formula (1) as an antagonist against a vanilloid receptor-1, a pharmaceutical composition comprising the same as an active ingredient, and a use thereof. The benzoxazine benzimidazole derivative of the present invention may be useful for preventing or treating a disease associated with antagonistic activity of vanilloid receptor-1: wherein, R1, R2, R3, R3′, Q1, Q2, Q3 and Q4 have same meanings as defined in the specification.

Abstract translation: 本发明涉及作为对香草素受体-1的拮抗剂的式（1）的新的苯并恶嗪苯并咪唑衍生物，包含其作为活性成分的药物组合物及其用途。 本发明的苯并恶嗪苯并咪唑衍生物可用于预防或治疗与香草素受体-1的拮抗活性相关的疾病：其中，R1，R2，R3，R3'，Q1，Q2，Q3和Q4具有与定义相同的含义 在规范中。

公开(公告)号：US07847416B2

公开(公告)日：2010-12-07

申请号：US12498913

申请日：2009-07-07

Applicant: Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang ,  Dong-Ho Lee ,  Seong-Deok Hwang

Inventor： Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang ,  Dong-Ho Lee ,  Seong-Deok Hwang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01093 ,  H01L2224/11 ,  H01L2224/05552

Abstract: Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.

Abstract translation: 提供了晶片级封装及其制造方法。 在一个实施例中，方法之一包括形成在晶片上具有连接焊盘的半导体芯片，图案化晶片的底表面以在连接焊盘下方形成沟槽，图案化沟槽的底表面以形成通孔， 并且通过通孔形成连接到连接垫的连接装置。 本发明提供了与传统封装相比，具有减小的厚度，较低的制造成本和增加的可靠性的晶片级封装。

公开(公告)号：US07830017B2

公开(公告)日：2010-11-09

申请号：US11950251

申请日：2007-12-04

Applicant: In-Young Lee ,  Dong-Ho Lee ,  Nam-Seog Kim ,  Hyun-Soo Chung ,  Ho-Jin Lee ,  Myeong-Soo Park

Inventor： In-Young Lee ,  Dong-Ho Lee ,  Nam-Seog Kim ,  Hyun-Soo Chung ,  Ho-Jin Lee ,  Myeong-Soo Park

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/525 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.

Abstract translation: 提供了其中在晶片级应用再分配处理的晶片级芯片级封装，其制造方法以及包括晶片级芯片级封装的半导体芯片模块。 晶片级芯片级封装包括具有接合焊盘的半导体芯片，设置在半导体芯片上以暴露焊盘的第一绝缘层，设置在暴露的焊盘和第一绝缘层上的再分配线，牺牲层 设置在所述再分配线的再分配衬垫的下方，设置在所述再分配线上的第二绝缘层，以暴露所述再分配衬垫并且包括设置在所述牺牲层旁边的裂纹诱导孔，以及附接到所述再分布衬垫的外部连接端子。

公开(公告)号：US07777345B2

公开(公告)日：2010-08-17

申请号：US12132925

申请日：2008-06-04

Applicant: Ho-Jin Lee ,  Nam-Seog Kim ,  Yong-Chai Kwon ,  Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang

Inventor： Ho-Jin Lee ,  Nam-Seog Kim ,  Yong-Chai Kwon ,  Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/034 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05011 ,  H01L2224/05552 ,  H01L2224/05559 ,  H01L2224/05561 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/00014

Abstract: A semiconductor device having a through electrode and a method of fabricating the same are disclosed. In one embodiment, a semiconductor device includes a first insulating layer formed on a semiconductor substrate. A wiring layer having a first aperture to expose a portion of the first insulating layer is formed on the first insulating layer. A second insulating layer is formed on an upper portion of the wiring layer and in the first aperture. A conductive pad having a second aperture to expose a portion of the second insulating layer is formed on the second insulating layer. A through hole with a width narrower than widths of the first and second apertures is formed through the first and second insulating layers and an upper portion of the semiconductor substrate. A through electrode is formed in the through hole.

Abstract translation: 公开了一种具有通孔的半导体器件及其制造方法。 在一个实施例中，半导体器件包括形成在半导体衬底上的第一绝缘层。 具有用于露出第一绝缘层的一部分的第一孔的布线层形成在第一绝缘层上。 第二绝缘层形成在布线层的上部和第一孔中。 具有第二孔径以暴露第二绝缘层的一部分的导电焊盘形成在第二绝缘层上。 通过第一和第二绝缘层和半导体衬底的上部形成宽度比第一和第二孔的宽度窄的通孔。 在通孔中形成贯通电极。

公开(公告)号：US07592709B2

公开(公告)日：2009-09-22

申请号：US11430900

申请日：2006-05-10

Applicant: Hyun-soo Chung ,  Dong-hyeon Jang ,  Dong-ho Lee ,  In-young Lee

Inventor： Hyun-soo Chung ,  Dong-hyeon Jang ,  Dong-ho Lee ,  In-young Lee

IPC: H01L23/48 ,  H01L29/40 ,  H01L23/28

CPC classification number: H01L23/3128 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19103 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A ball grid array type board on chip package may include an integrated circuit chip having an active surface that supports a plurality of contact pads. An interposer may be adhered to the active surface of the integrated circuit chip. At least one hole may be provided through the interposer to expose the contact pads. A board, which may have a first surface supporting a plurality of metal lines, may have a second surface adhered to the interposer. The board may have an opening through which the contact pads may be exposed. A plurality of bonding wires may connect the contact pads to the metal lines through the opening.

Abstract translation: 球栅阵列型片上芯片封装可以包括具有支撑多个接触焊盘的有源表面的集成电路芯片。 插入器可以粘附到集成电路芯片的有源表面。 可以通过插入件提供至少一个孔以暴露接触垫。 可以具有支撑多个金属线的第一表面的板可以具有粘附到插入件的第二表面。 板可以具有开口，接触垫可以穿过该开口露出。 多个接合线可以通过开口将接触垫连接到金属线。

公开(公告)号：US20080150089A1

公开(公告)日：2008-06-26

申请号：US11979562

申请日：2007-11-06

Applicant: Yong-Chai Kwon ,  Dong-Ho Lee ,  In-Young Lee

Inventor： Yong-Chai Kwon ,  Dong-Ho Lee ,  In-Young Lee

IPC: H01L23/48 ,  H01L21/4763

CPC classification number: H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A method of fabricating a semiconductor device is provided. The method may include forming an insulating layer on a wafer. The wafer may have an active surface and an inactive surface which face each other, and the insulating layer may be formed on the active surface. A pad may be formed on the insulating layer, and a first hole may be formed in the insulating layer. A first hole insulating layer may then be formed on an inner wall of the first hole. A second hole may be formed under the first hole. The second hole may be formed to extend from the first hole into the wafer. A second hole insulating layer may be formed on an inner wall of the second hole. The semiconductor device fabricated according to the method may also be provided.

Abstract translation: 提供一种制造半导体器件的方法。 该方法可以包括在晶片上形成绝缘层。 晶片可以具有彼此面对的有源表面和非活性表面，并且绝缘层可以形成在有源表面上。 可以在绝缘层上形成焊盘，并且可以在绝缘层中形成第一孔。 然后可以在第一孔的内壁上形成第一孔绝缘层。 可以在第一孔下方形成第二孔。 第二孔可以形成为从第一孔延伸到晶片。 第二孔绝缘层可以形成在第二孔的内壁上。 还可以提供根据该方法制造的半导体器件。

公开(公告)号：US20070269931A1

公开(公告)日：2007-11-22

申请号：US11752219

申请日：2007-05-22

Applicant: Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang ,  Dong-Ho Lee ,  Seong-Deok Hwang

Inventor： Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang ,  Dong-Ho Lee ,  Seong-Deok Hwang

IPC: H01L21/00

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01093 ,  H01L2224/11 ,  H01L2224/05552

Abstract: Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.

Abstract translation: 提供了晶片级封装及其制造方法。 在一个实施例中，方法之一包括形成在晶片上具有连接焊盘的半导体芯片，图案化晶片的底表面以在连接焊盘下方形成沟槽，图案化沟槽的底表面以形成通孔， 并且通过通孔形成连接到连接垫的连接装置。 本发明提供了与传统封装相比，具有减小的厚度，较低的制造成本和增加的可靠性的晶片级封装。