公开(公告)号：US08124880B2

公开(公告)日：2012-02-28

申请号：US11976207

申请日：2007-10-22

Applicant: Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

Inventor： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC: H05K1/03

CPC classification number: H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

Abstract: A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.

Abstract translation: 一种电路板的制造方法，其特征在于，包括：在堆叠在载体上的种子层上，形成导电消除图案，所述导电解像图案包括依次与第一电路图案对应地层叠的第一镀层，第一金属层和第二镀层 ; 将载体和绝缘体堆叠并压在一起，使得具有导电缓冲图案的载体的表面面向绝缘体; 通过移除载体将导电释放图案转印到绝缘体中; 在具有转印的导电消除图案的绝缘体的表面上形成包括与第二电路图案顺序堆叠的第三镀层和第二金属层的导电图案; 去除第一镀层和籽晶层; 并且去除第一和第二金属层可以提供具有高密度电路图案而不增加绝缘体量的电路板。

公开(公告)号：US20110308845A1

公开(公告)日：2011-12-22

申请号：US13164055

申请日：2011-06-20

Applicant: Suk Hyeon CHO ,  Jung Hyun Park

Inventor： Suk Hyeon CHO ,  Jung Hyun Park

IPC: H05K1/09 ,  H05K3/42 ,  H05K1/11

CPC classification number: H05K3/421 ,  H05K3/0097 ,  H05K3/426 ,  H05K3/427 ,  H05K2201/0959 ,  H05K2203/1536 ,  Y10T29/49165

Abstract: The present invention provides a printed circuit board including: an insulating member having a through via hole; a circuit pattern disposed on the insulating member; a solder resist disposed on the insulating member while exposing a portion of the circuit pattern; a via plating pad connected to the circuit pattern, disposed inside the via hole, and covering a lower opening of the via hole along an inner wall of the via hole; and an external connection means having a center portion coinciding with a center portion of the via hole and disposed on the via plating pad, and a method of manufacturing the same.

Abstract translation: 本发明提供一种印刷电路板，包括：具有通孔的绝缘件; 布置在所述绝缘构件上的电路图案; 设置在所述绝缘构件上的阻焊剂，同时暴露所述电路图案的一部分; 连接到所述电路图案的通孔电镀垫，设置在所述通孔内部，并且沿着所述通孔的内壁覆盖所述通孔的下开口; 以及具有与通孔的中心部分重合并设置在通孔电镀垫上的中心部分的外部连接装置及其制造方法。

公开(公告)号：US20110221074A1

公开(公告)日：2011-09-15

申请号：US13067219

申请日：2011-05-17

Applicant: Myung-Sam Kang ,  Chang-Sup Ryu ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

Inventor： Myung-Sam Kang ,  Chang-Sup Ryu ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC: H01L23/488

CPC classification number: H01L23/3128 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A board on chip package including a photo solder resist having a cavity and a pattern on one side, the pattern corresponding to a circuit wire; a solder ball pad accommodated in the cavity; a circuit wire electrically connected with the solder ball pad, and formed on the other side of the photo solder resist; a semiconductor chip mounted on the solder ball pad by a flip chip bonding; and a passivation material to mold the semiconductor chip.

Abstract translation: 一种片上封装，包括具有空腔和一侧图案的光阻焊剂，该图案对应于电路线; 容纳在腔中的焊球垫; 与焊锡球焊盘电连接并形成在光阻焊剂的另一侧上的电路线; 通过倒装芯片焊接安装在焊球垫上的半导体芯片; 以及用于模制半导体芯片的钝化材料。

公开(公告)号：US20110159881A1

公开(公告)日：2011-06-30

申请号：US12895190

申请日：2010-09-30

Applicant: Won Jae Shin ,  Young-Jun Hong ,  Jung Hyun Park ,  Chang Yong Shin ,  Dong Jo Park

Inventor： Won Jae Shin ,  Young-Jun Hong ,  Jung Hyun Park ,  Chang Yong Shin ,  Dong Jo Park

IPC: H04W72/04

CPC classification number: H04B7/024

Abstract: A communication method for at least one mobile station that includes a target mobile station that performs a Cooperative Multi-Point (CoMP) communication with at least two base stations, is provided. The communication method includes determining a beamforming vector used by the at least two base stations based on channel vectors and at least one channel matrix such that a signal-to-leakage-plus-noise-ratio (SLNR) for a target antenna from among antennas of a target mobile station is maximized. A Cholesky factorization may be used to determine an optimal beamforming vector with a low complexity.

Abstract translation: 提供一种用于至少一个移动站的通信方法，该移动站包括与至少两个基站进行协作多点（CoMP）通信的目标移动站。 通信方法包括基于信道向量和至少一个信道矩阵确定由至少两个基站使用的波束成形向量，使得从天线中的目标天线的信号与泄漏加噪声比（SLNR） 目标移动台的最大化。 可以使用Cholesky因式分解来确定具有低复杂度的最优波束形成向量。

公开(公告)号：US20110095425A1

公开(公告)日：2011-04-28

申请号：US12923037

申请日：2010-08-30

Applicant: Jung Hyun Park ,  Nam Keun Oh ,  Sang Duck Kim ,  Jong Gyu Choi ,  Young Ji Kim ,  Ji Eun Kim ,  Myung Sam Kang

Inventor： Jung Hyun Park ,  Nam Keun Oh ,  Sang Duck Kim ,  Jong Gyu Choi ,  Young Ji Kim ,  Ji Eun Kim ,  Myung Sam Kang

IPC: H01L23/498 ,  H01L21/768 ,  H01L21/50

CPC classification number: H01L21/76885 ,  H01L21/02112 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Provided is a ball grid array substrate, a semiconductor chip package, and a method of manufacturing the same. The ball grid array substrate includes an insulating layer having a first surface providing a mounting region for a semiconductor chip, a second surface opposing the first surface, and an opening connecting the second surface with the mounting region of the semiconductor chip, and a circuit pattern buried in the second surface. Since the ball grid array substrate is manufactured by a method of stacking two insulating layers, existing devices can be used, and the ball grid array substrate can be manufactured as an ultra thin plate. In addition, since the circuit pattern is buried in the insulating layer, a high-density circuit pattern can be formed.

Abstract translation: 提供了一种球栅阵列基板，半导体芯片封装及其制造方法。 球栅阵列基板包括绝缘层，其具有提供半导体芯片的安装区域的第一表面，与第一表面相对的第二表面和连接第二表面与半导体芯片的安装区域的开口，以及电路图案 埋在第二面。 由于球栅阵列基板通过堆叠两个绝缘层的方法制造，因此可以使用现有的装置，并且可以将球栅阵列基板制造为超薄板。 此外，由于电路图案被埋在绝缘层中，因此可以形成高密度电路图案。

公开(公告)号：USD618193S1

公开(公告)日：2010-06-22

申请号：US29270444

申请日：2006-12-22

Applicant: Jung Yong Lee ,  Matias Duarte ,  Sang Kyun Kim ,  Jung-Hyun Park

Designer： Jung Yong Lee ,  Matias Duarte ,  Sang Kyun Kim ,  Jung-Hyun Park

公开(公告)号：USD606060S1

公开(公告)日：2009-12-15

申请号：US29270443

申请日：2006-12-22

Applicant: Jung Yong Lee ,  Matias Duarte ,  Sang Kyun Kim ,  Jung-Hyun Park

Designer： Jung Yong Lee ,  Matias Duarte ,  Sang Kyun Kim ,  Jung-Hyun Park

公开(公告)号：US07562446B2

公开(公告)日：2009-07-21

申请号：US11524403

申请日：2006-09-21

Applicant: Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H05K3/4652 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/183 ,  H05K3/0097 ,  H05K3/205 ,  H05K3/4697 ,  H05K2201/09536 ,  H05K2203/0191 ,  H05K2203/063 ,  H05K2203/308 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015

Abstract: A method for manufacturing a substrate having a cavity is disclosed. The method comprises: (a) forming a first circuit patter on both sides of a seed layer by use of a first dry film, the seed layer being for forming a circuit pattern on both sides; (b) laminating a second dry film on the first dry film on both sides of the seed layer, the thickness of the second dry film corresponding to the depth of the cavity to be formed; (c) laminating a dielectric layer on an area outside of where the cavity is to be formed on both sides of the seed layer, the thickness of the dielectric layer corresponding to the depth of the cavity to be formed; (d) laminating on the seed layer a copper foil laminated master having a second circuit pattern; and (e) forming the cavity by peeling off the first dry film and the second dry film after removing the seed layer. The method for manufacturing a substrate with a cavity in accordance with the present invention can improve the efficiency of a substrate manufacturing process by using both sides of a seed layer to manufacture the substrate with a cavity.

Abstract translation: 公开了一种用于制造具有空腔的衬底的方法。 该方法包括：（a）通过使用第一干膜在种子层的两侧形成第一电路图案，种子层用于在两侧形成电路图案; （b）在种子层两侧的第一干膜上层叠第二干膜，第二干膜的厚度对应于待形成的空腔的深度; （c）在种子层的两侧上在要形成空腔的区域之外的区域层叠电介质层，电介质层的厚度对应于待形成的空腔的深度; （d）在种子层上层叠具有第二电路图案的铜箔层叠主板; 和（e）通过在去除种子层之后剥离第一干膜和第二干膜来形成空腔。 根据本发明的用于制造具有空腔的基板的方法可以通过使用种子层的两面来制造具有空腔的基板来提高基板制造工艺的效率。

公开(公告)号：US07516545B2

公开(公告)日：2009-04-14

申请号：US11591586

申请日：2006-11-02

Applicant: Myung Sam Kang ,  Shuhichi Okabe ,  Jung Hyun Park ,  Hoe Ku Jung ,  Ji Eun Kim

Inventor： Myung Sam Kang ,  Shuhichi Okabe ,  Jung Hyun Park ,  Hoe Ku Jung ,  Ji Eun Kim

IPC: H01K3/10 ,  H05K3/02

CPC classification number: H05K1/116 ,  H05K3/0094 ,  H05K3/421 ,  H05K3/428 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/0959 ,  H05K2203/0361 ,  H05K2203/0384 ,  H05K2203/0542 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49133 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Disclosed is a method of manufacturing a printed circuit board having a landless via hole. Specifically, this invention provides a method of manufacturing a printed circuit board having a landless via hole without the upper land of a via hole using a photoresist (P-LPR) which is loaded in the via hole. Therefore, in this invention, since a circuit pattern is formed using only copper of a copper clad laminate, the width thereof is minimized, thus easily realizing a fine circuit pattern. Further, the landless via hole structure is applied, resulting in a highly dense circuit pattern.

Abstract translation: 公开了一种具有无地过孔的印刷电路板的制造方法。 具体而言，本发明提供一种制造印刷电路板的方法，所述印刷电路板具有无通孔通孔，所述无通孔通孔使用装载在所述通孔中的光致抗蚀剂（P-LPR）而不具有通孔的上部焊盘。 因此，在本发明中，由于仅使用覆铜层压板的铜形成电路图案，所以其宽度被最小化，因此容易实现精细电路图案。 此外，施加无地通孔结构，导致高度密集的电路图案。

公开(公告)号：US20090056119A1

公开(公告)日：2009-03-05

申请号：US12005610

申请日：2007-12-28

Applicant: Shuhichi Okabe ,  Je Gwang Yoo ,  Chang Sup Ryu ,  Myung Sam Kang ,  Jung Hyun Park ,  Ji Hong Jo ,  Jin Yong An ,  Soon Oh Jung

Inventor： Shuhichi Okabe ,  Je Gwang Yoo ,  Chang Sup Ryu ,  Myung Sam Kang ,  Jung Hyun Park ,  Ji Hong Jo ,  Jin Yong An ,  Soon Oh Jung

IPC: H05K3/00

CPC classification number: H05K3/205 ,  H05K3/062 ,  H05K3/108 ,  H05K3/462 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2203/0369 ,  H05K2203/061 ,  H05K2203/0733 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Disclosed is a method of fabricating a multilayer printed circuit board, which enables the formation of a micro circuit able to be realized through a semi-additive process using the CTE and rigidity of a metal carrier on a thin substrate which is difficult to convey.

Abstract translation: 公开了一种制造多层印刷电路板的方法，其能够形成能够通过使用CTE的半添加工艺和难以传送的薄基板上的金属载体的刚性来实现的微电路。