公开(公告)号：US08035951B2

公开(公告)日：2011-10-11

申请号：US12805886

申请日：2010-08-23

Applicant: Shih-Hsien Wu ,  Shinn-Juh Lai ,  Min-Lin Lee ,  Shur-Fen Liu

Inventor： Shih-Hsien Wu ,  Shinn-Juh Lai ,  Min-Lin Lee ,  Shur-Fen Liu

IPC: H01G4/06

CPC classification number: H01G4/06 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/14 ,  H01G4/20 ,  H01G4/206 ,  H05K1/162 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/09672 ,  H05K2201/2036 ,  Y10T29/417

Abstract: A capacitor device with a capacitance is introduced. The capacitor device includes at least one capacitive element. The at least capacitive element comprises a pair of first conductive layers being opposed to each other, at least one first dielectric layer formed on a surface of at least one of the first conductive layers, and a second dielectric layer being sandwiched between the first conductive layers. The first dielectric layer has a first dielectric constant and the second dielectric layer has a second dielectric constant. The capacitance of the capacitor device depends on dielectric parameters of the first dielectric layer and the second dielectric layer. The dielectric parameters comprise the first dielectric constant and thickness of the at least one first dielectric layer and the second dielectric constant and thickness of the second dielectric layer.

Abstract translation: 引入具有电容的电容器件。 电容器装置包括至少一个电容元件。 所述至少电容元件包括彼此相对的一对第一导电层，至少一个形成在所述第一导电层中的至少一个的表面上的第一电介质层，以及夹在所述第一导电层 。 第一介电层具有第一介电常数，第二介电层具有第二介电常数。 电容器器件的电容取决于第一介电层和第二介电层的介电参数。 介电参数包括第一介电常数和至少一个第一介电层的厚度和第二介电常数和第二介电层的厚度。

公开(公告)号：US08035036B2

公开(公告)日：2011-10-11

申请号：US11861297

申请日：2007-09-26

Applicant: Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

Inventor： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

IPC: H05K1/16

CPC classification number: H05K1/167 ,  H05K1/0224 ,  H05K1/025 ,  H05K1/0298 ,  H05K2201/0792 ,  H05K2201/09681 ,  H05K2201/0969

Abstract: A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.

Abstract translation: 提供了一种互补镜像嵌入式平面电阻架构。 在该结构中，在接地平面或电极平面上形成互补的中空结构以最小化寄生电阻，从而有效地提高施加频率。 此外，在某些情况下，一些信号传输线通过嵌入式平面电阻器下方的位置，如果根本没有屏蔽，则会发生严重的干扰或串扰现象。 因此，将接地平面，电极平面或与嵌入式平面电阻器相邻的功率层的互补空心结构设计为网格结构，以减少干扰或串扰现象。 以这种方式，整个电阻器结构在电路中具有优选的高频电特性。

公开(公告)号：US07894178B2

公开(公告)日：2011-02-22

申请号：US12046422

申请日：2008-03-11

Applicant: Bang-Hao Wu ,  Li-Duan Tsai ,  Min-Lin Lee ,  Cheng-Liang Cheng

Inventor： Bang-Hao Wu ,  Li-Duan Tsai ,  Min-Lin Lee ,  Cheng-Liang Cheng

IPC: H01G9/04 ,  H01G9/145 ,  H01G4/228

CPC classification number: H05K1/162 ,  H01G9/012 ,  H01G11/48 ,  H05K2201/09809 ,  H05K2203/0315 ,  Y02E60/13 ,  Y10T29/417 ,  Y10T29/435

Abstract: A through hole capacitor at least including a substrate, an anode layer, a dielectric layer, a first cathode layer, and a second cathode layer is provided. The substrate has a plurality of through holes. The anode layer is disposed on the inner surface of at least one through hole, and the surface of the anode layer is a porous structure. The dielectric layer is disposed on the porous structure of the anode layer. The first cathode layer covers a surface of the dielectric layer. The second cathode layer covers a surface of the first cathode layer, and the conductivity of the second cathode layer is greater than that of the first cathode layer. The through hole capacitor can be used for impedance control, as the cathode layers of the through hole are used for signal transmission.

Abstract translation: 提供至少包括基板，阳极层，电介质层，第一阴极层和第二阴极层的通孔电容器。 基板具有多个通孔。 阳极层设置在至少一个通孔的内表面上，阳极层的表面是多孔结构。 电介质层设置在阳极层的多孔结构上。 第一阴极层覆盖电介质层的表面。 第二阴极层覆盖第一阴极层的表面，第二阴极层的导电性大于第一阴极层的导电率。 通孔电容器可用于阻抗控制，因为通孔的阴极层用于信号传输。

公开(公告)号：US07649723B2

公开(公告)日：2010-01-19

申请号：US12047283

申请日：2008-03-12

Applicant: Chen-Hsuan Chiu ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Shih-Hsien Wu ,  Chi-Liang Pan

Inventor： Chen-Hsuan Chiu ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Shih-Hsien Wu ,  Chi-Liang Pan

IPC: H02H9/00 ,  H02H3/20 ,  H02H9/04 ,  H02H3/22 ,  H02H1/00 ,  H02H1/04 ,  H02H9/06

CPC classification number: H01L23/60 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2224/05599

Abstract: An ESD protection substrate is disclosed. The ESD protection substrate includes a first conductor, a second conductor, a pointed structure, and an ESD protection material. The pointed structure is electrically connected to the first or the second conductor. The ESD protection material is disposed between the first and the second conductors.

Abstract translation: 公开了ESD保护衬底。 ESD保护衬底包括第一导体，第二导​​体，尖锐结构和ESD保护材料。 尖的结构电连接到第一或第二导体。 ESD保护材料设置在第一和第二导体之间。

公开(公告)号：US20090210055A1

公开(公告)日：2009-08-20

申请号：US12211829

申请日：2008-09-17

Applicant: Tao-Chih Chang ,  Min-Lin Lee

Inventor： Tao-Chih Chang ,  Min-Lin Lee

IPC: A61F2/14

CPC classification number: A61F9/08 ,  A61F2/141 ,  A61N1/36046

Abstract: An artificial retina chip module including a signal processing chip, a first polymer bump layer, and a photodiode array chip is provided. The signal processing chip includes a plurality of first pad disposed on a surface thereof. The first polymer bump layer includes a plurality of polymer bumps insulated from one another. Each of the first polymer bumps is composed of a polymer material and a conductive layer coated on the polymer material. Each first polymer bump is embedded into the corresponding first pad and the signal processing chip, wherein one end of the first polymer bump protrudes from the first pad and the other end thereof protrudes from a back surface of the signal processing chip. The photodiode array chip is disposed at one side of the signal processing chip and is electrically connected to the signal processing chip through the first polymer bumps.

Abstract translation: 提供了包括信号处理芯片，第一聚合物凸块层和光电二极管阵列芯片的人造视网膜芯片模块。 信号处理芯片包括设置在其表面上的多个第一焊盘。 第一聚合物凸块层包括彼此绝缘的多个聚合物凸块。 每个第一聚合物凸块由聚合物材料和涂覆在聚合物材料上的导电层组成。 每个第一聚合物凸块被嵌入到相应的第一焊盘和信号处理芯片中，其中第一聚合物凸块的一端从第一焊盘凸出并且另一端从信号处理芯片的后表面突出。 光电二极管阵列芯片设置在信号处理芯片的一侧，并通过第一聚合物凸块与信号处理芯片电连接。

公开(公告)号：US20080239622A1

公开(公告)日：2008-10-02

申请号：US11950381

申请日：2007-12-04

Applicant: Chien-Min HSU ,  Shih-Hsien WU ,  Min-Lin LEE ,  Shinn-Juh LAI

Inventor： Chien-Min HSU ,  Shih-Hsien WU ,  Min-Lin LEE ,  Shinn-Juh LAI

IPC: H01G4/236 ,  H05K1/16

CPC classification number: H05K1/162 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/112 ,  H05K3/429 ,  H05K3/4688 ,  H05K2201/0792 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09636 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: The present invention relates to a wiring structure for reducing the equivalent series inductance (ESL) of a laminated capacitor. The laminated capacitor comprises a number of conductive layers, a power via extending along a thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer, and a ground via extending along the thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer. The conductive layers include a set of first conductive layers and a set of second conductive layers. The power via is electrically coupled to the first conductive layers and the ground via is electrically coupled to the second conductive layers. The laminated capacitor further comprises a supplemental via between the power via and the ground via. The supplemental via is shorter in length than the power via and the ground via. The supplemental via is electrically coupled to one of the first conductive layers and the second conductive layer.

Abstract translation: 本发明涉及一种用于降低层叠电容器的等效串联电感（ESL）的布线结构。 层叠电容器包括多个导电层，沿层叠电容器的厚度方向延伸的电力通孔，并且从顶部导电层延伸至底部导电层，沿着层叠电容器的厚度方向延伸的接地通孔 并布置成从顶部导电层延伸到底部导电层。 导电层包括一组第一导电层和一组第二导电层。 电源通孔电耦合到第一导电层，并且接地通孔电耦合到第二导电层。 层叠电容器还包括电源通孔和接地通孔之间的补充通路。 补充通孔的长度要短于电源通孔和接地通孔。 辅助通孔电耦合到第一导电层和第二导电层之一。

公开(公告)号：US20070164396A1

公开(公告)日：2007-07-19

申请号：US11646339

申请日：2006-12-28

Applicant: Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Ying-Jiunn Lai

Inventor： Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Ying-Jiunn Lai

IPC: H01L29/00

CPC classification number: H01L23/14 ,  H01F17/0006 ,  H01F41/046 ,  H01F2017/0066 ,  H01G4/30 ,  H01G4/40 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49894 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/086 ,  H05K2201/09672 ,  H01L2924/00

Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.

Abstract translation: 提供了多功能复合基板结构。 具有高介电常数的第一衬底和具有低介电常数和低损耗角正切的第二衬底交错在第三衬底之上。 一个或多个导磁块可以形成在每个衬底之上，使得可以在其上制造一个或多个电感器。 可以在第一基板上制造一个或多个电容器。 此外，系统阻抗的一个或多个信号传输迹线形成在外层的第二基板上。 因此，有效地提高了电感器的电感。 此外，内置组件的面积减少。 此外，它具有更短的延迟时间，更小的介电损耗和更高的传输高速和高频信号的回波损耗。

公开(公告)号：US20070062726A1

公开(公告)日：2007-03-22

申请号：US11531337

申请日：2006-09-13

Applicant: Huey-Ru Chang ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin Sun Shyu

Inventor： Huey-Ru Chang ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin Sun Shyu

IPC: H05K1/16

CPC classification number: H01L23/50 ,  H01G4/38 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/01079 ,  H05K1/0231 ,  H05K1/162 ,  H05K2201/09309 ,  H05K2201/10734

Abstract: An embedded capacitor device within a circuit board having an integrated circuitry thereon is provided. The circuit board has a common coupling area under the integrated circuitry. The embedded capacitor device includes a first capacitor section providing at least one capacitor to a first terminal set of the integrated circuitry and a second capacitor section providing at least one capacitor to a second terminal set of the integrated circuitry. A portion of the first capacitor section is in the common coupling area and has its coupling to the first terminal set located in the common coupling area. Similarly, a portion of the second capacitor section is in the common coupling area and has its coupling to the second terminal set located in the common coupling area.

Abstract translation: 提供了具有集成电路的电路板内的嵌入式电容器件。 电路板在集成电路下具有公共耦合区域。 嵌入式电容器装置包括：向集成电路的第一端子组提供至少一个电容器的第一电容器部分和向集成电路的第二端子组提供至少一个电容器的第二电容器部分。 第一电容器部分的一部分在公共耦合区域中，并且其耦合到位于公共耦合区域中的第一端子组。 类似地，第二电容器部分的一部分在公共耦合区域中，并且其耦合到位于公共耦合区域中的第二端子组。

公开(公告)号：US20050146840A1

公开(公告)日：2005-07-07

申请号：US11039924

申请日：2005-01-24

Applicant: Min-Lin Lee ,  Chin-Sun Shyu ,  Shur-Fen Liu ,  Jing-Pin Pan ,  Jinn-Shing King

Inventor： Min-Lin Lee ,  Chin-Sun Shyu ,  Shur-Fen Liu ,  Jing-Pin Pan ,  Jinn-Shing King

IPC: H01G4/20 ,  H01G4/35 ,  H05K1/16

CPC classification number: H01G4/35 ,  H01G4/20 ,  H05K1/162 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/0355

Abstract: An interleaving striped capacitor substrate structure for pressing-type print circuit boards is disclosed. To meet the high-frequency, high-speed, and high-density requirements in modern electronic systems, the interleaving striped capacitor substrate structure uses several dielectric materials of different dielectric coefficients to make a dielectric layer. One dielectric layer can be stacked on another to form a multi-layered capacitor substrate so that a single capacitor substrate can provide the highest capacitance required for the decoupling capacitor to suppress high-frequency noise signals, and the lower dielectric coefficient substrate required for high-speed signal transmission. This simultaneously achieves the effects of reducing high-frequency transmission time and suppressing high-frequency noise.

Abstract translation: 公开了一种用于按压式印刷电路板的交错条纹电容器基底结构。 为了满足现代电子系统的高频，高速和高密度要求，交错条纹电容器基板结构使用不同介电系数的几种介电材料制成介电层。 一个电介质层可以堆叠在另一个上以形成多层电容器基板，使得单个电容器基板可以提供去耦电容器所需的最高电容以抑制高频噪声信号，并且高电平基板所需的低介电系数基板， 速度信号传输。 这同时实现了降低高频传输时间并抑制高频噪声的效果。

公开(公告)号：US09030808B2

公开(公告)日：2015-05-12

申请号：US13607820

申请日：2012-09-10

Applicant: Chien-Min Hsu ,  Min-Lin Lee ,  Li-Duan Tsai

Inventor： Chien-Min Hsu ,  Min-Lin Lee ,  Li-Duan Tsai

IPC: H01G5/38 ,  H01G9/04 ,  H05K1/16 ,  H01G9/012 ,  H01G9/15 ,  H01G9/26 ,  H05K1/02 ,  H05K1/05

CPC classification number: H05K1/162 ,  H01G9/012 ,  H01G9/04 ,  H01G9/15 ,  H01G9/26 ,  H05K1/0231 ,  H05K1/053 ,  H05K2201/0116 ,  H05K2201/0175 ,  H05K2201/0191 ,  H05K2201/0323 ,  H05K2201/0329 ,  H05K2201/0338 ,  H05K2201/09063 ,  H05K2201/10522 ,  H05K2203/0307 ,  H05K2203/0315 ,  H05K2203/0369 ,  H05K2203/0723

Abstract: A capacitor and a circuit board having the same are provided. The capacitor includes a substrate, an oxide layer, a second electrode, an insulating layer, a plurality of conductive sheets and a plurality of vias. The substrate includes a first electrode and a porous structure. The porous structure in at least of two distribution regions has different depths. An oxide layer is disposed on the surface of the porous structure. The second electrode is disposed on the oxide layer and includes a conductive polymer material. The insulating layer disposed on the second electrode has a third and a fourth surfaces. The fourth surface of the insulating layer is connected with the second electrode. The conductive sheets are disposed on the first surface of the first electrode and the third surface of the insulating layer and electrically connected with the corresponding vias according to different polarities.

Abstract translation: 提供电容器和具有该电容器的电路板。 电容器包括衬底，氧化物层，第二电极，绝缘层，多个导电片和多个通孔。 基板包括第一电极和多孔结构。 至少两个分布区域中的多孔结构具有不同的深度。 氧化物层设置在多孔结构的表面上。 第二电极设置在氧化物层上并且包括导电聚合物材料。 设置在第二电极上的绝缘层具有第三和第四表面。 绝缘层的第四表面与第二电极连接。 导电片设置在第一电极的第一表面和绝缘层的第三表面上，并根据不同的极性与相应的通孔电连接。