公开(公告)号：US09299647B2

公开(公告)日：2016-03-29

申请号：US14181105

申请日：2014-02-14

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Kevin Matthew Durocher ,  Scott Smith ,  Donald Paul Cunningham

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/92144 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads.

Abstract translation: 用于嵌入式芯片封装的互连组件包括介电层，包括上接触焊盘的第一金属层，包括下接触焊盘的第二金属层和通过介电层形成并与上接触焊盘和下接触焊盘接触的金属化连接，以形成电 它们之间的连接。 上接触焊盘的第一表面固定到电介质层的顶表面，并且下接触焊盘的第一表面固定到电介质层的底表面。 互连组件的第一侧的输入/输出（I / O）形成在下接触焊盘的与下接触焊盘的第一表面相对的表面上，并且第二侧的I / O 互连组件形成在与上接触焊盘的第一表面相对的上接触焊盘的表面上。

公开(公告)号：US20160056136A1

公开(公告)日：2016-02-25

申请号：US14464877

申请日：2014-08-21

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L23/538 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76897 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/538 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/83865 ,  H01L2224/83874 ,  H01L2224/83895 ,  H01L2224/83931 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/20 ,  H01L2924/014 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00012

Abstract: An electronics package includes a first dielectric substrate having a first plurality of vias formed through a thickness thereof, a metalized contact layer coupled to a top surface of the first dielectric substrate, and a first die positioned within a first die opening formed through the thickness of the first dielectric substrate. Metalized interconnects are formed on a bottom surface of the first dielectric substrate and extend through the first plurality of vias to contact the metalized contact layer. A second dielectric substrate is coupled to the first dielectric substrate and has a second plurality of vias formed through a thickness thereof. Metalized interconnects extend through the second plurality of vias to contact the first plurality of metalized interconnects and contact pads of the first die. A first conductive element electrically couples the first die to the metalized contact layer.

Abstract translation: 一种电子封装包括：第一介电基片，具有通过其厚度形成的第一多个通孔;金属化接触层，其耦合到第一电介质基板的顶表面;以及第一裸片，位于第一裸片开口内， 第一电介质基片。 金属化互连件形成在第一电介质基片的底表面上并延伸通过第一多个通孔以接触金属化的接触层。 第二电介质基板耦合到第一电介质基板，并且具有通过其厚度形成的第二多个通孔。 金属化互连延伸穿过第二多个通孔以接触第一裸片的第一多个金属化互连和接触垫。 第一导电元件将第一裸片电耦合到金属化接触层。

公开(公告)号：US20150287699A1

公开(公告)日：2015-10-08

申请号：US14742773

申请日：2015-06-18

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6836 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/27003 ,  H01L2224/27312 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/2741 ,  H01L2224/27416 ,  H01L2224/27418 ,  H01L2224/27422 ,  H01L2224/27436 ,  H01L2224/2781 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/94 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/3511 ,  H05K3/305 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2224/19 ,  H01L21/78 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A chip package includes a first die with an active surface having at least one die pad positioned thereon; a first adhesive layer having a first surface coupled to the active surface of the first die and a second surface opposite the first surface; and a first dielectric layer having a top surface. A first portion of the top surface of the first dielectric layer is coupled to the second surface of the first adhesive layer. A second portion of the top surface of the first dielectric layer, distinct from the first portion, is substantially free of adhesive.

Abstract translation: 芯片封装包括具有活性表面的第一裸片，其中至少一个芯片焊盘位于其上; 第一粘合剂层，其具有联接到第一管芯的有效表面的第一表面和与第一表面相对的第二表面; 以及具有顶表面的第一电介质层。 第一电介质层的顶表面的第一部分耦合到第一粘合剂层的第二表面。 与第一部分不同的第一介电层的顶表面的第二部分基本上没有粘合剂。

公开(公告)号：US20150171036A1

公开(公告)日：2015-06-18

申请号：US14625744

申请日：2015-02-19

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee ,  Kevin Matthew Durocher ,  Scott Smith ,  Donald Paul Cunningham

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L23/481 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/92144 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00

Abstract: A chip package includes a first substrate having at least one circuit layer formed on a first surface thereof, a first die mounted on a second surface of the first substrate opposite from the first surface, and an interconnection assembly comprising upper and lower conductive layers provided on an insulating substrate, with the upper conductive layer of the interconnection assembly affixed to the second surface of the first substrate and electrically connected to the at least one circuit layer of the first substrate. A second substrate is positioned on a side of the first die opposite from the first substrate so as to position the die between the first and second substrates, the second substrate having at least one circuit layer formed on an outward facing first surface thereof that is electrically connected to at least one of the lower conductive layers of the interconnection assembly and the first die.

Abstract translation: 芯片封装包括：第一基板，其具有在其第一表面上形成的至少一个电路层，安装在第一基板的与第一表面相对的第二表面上的第一裸片;以及互连组件，其包括设置在第一基板上的上下导电层 绝缘基板，其中互连组件的上导电层固定到第一基板的第二表面并电连接到第一基板的至少一个电路层。 第二基板位于与第一基板相对的第一模具的一侧上，以便将模具定位在第一和第二基板之间，第二基板具有形成在其面向外的第一表面上的至少一个电路层， 连接到互连组件和第一模具的至少一个下导电层。

公开(公告)号：US20150084207A1

公开(公告)日：2015-03-26

申请号：US14037728

申请日：2013-09-26

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Paul Alan McConnelee ,  Arun Virupaksha Gowda

IPC: H01L23/522 ,  H01L23/42 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/433 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/25 ,  H01L24/26 ,  H01L24/32 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/2518 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0266 ,  H05K1/185 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

公开(公告)号：US20150069612A1

公开(公告)日：2015-03-12

申请号：US14547667

申请日：2014-11-19

Applicant: General Electric Company

Inventor： Shakti Singh Chauhan ,  Arun Virupaksha Gowda ,  Paul Alan McConnelee

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/3178 ,  H01L23/3735 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L24/95 ,  H01L25/072 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/8384 ,  H01L2224/92144 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.

Abstract translation: 公开了一种表面贴装封装结构，其提供了改善的热机械可靠性和更坚固的二级封装互连。 表面贴装封装结构包括具有电介质层的子模块，附着到电介质层的半导体器件，电耦合到半导体器件的第一级金属互连结构以及电耦合到第一级的第二级I / O连接 互连并形成在与半导体器件相对的一侧的电介质层上，其中第二级I / O连接被配置为将子模块连接到外部电路。 子模块的半导体器件附接到多层衬底结构的第一表面，其中介电材料位于介电层和多层衬底结构之间以填充表面安装结构中的间隙，并提供 额外的结构完整性。

公开(公告)号：US20140159213A1

公开(公告)日：2014-06-12

申请号：US14181105

申请日：2014-02-14

Applicant: General Electric Company

Inventor： Paul Alan McConnelee ,  Kevin Matthew Durocher ,  Scott Smith ,  Donald Paul Cunningham

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/92144 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads.

Abstract translation: 用于嵌入式芯片封装的互连组件包括介电层，包括上接触焊盘的第一金属层，包括下接触焊盘的第二金属层和通过介电层形成并与上接触焊盘和下接触焊盘接触的金属化连接，以形成电 它们之间的连接。 上接触焊盘的第一表面固定到电介质层的顶表面，并且下接触焊盘的第一表面固定到电介质层的底表面。 互连组件的第一侧的输入/输出（I / O）形成在下接触焊盘的与下接触焊盘的第一表面相对的表面上，并且第二侧的I / O 互连组件形成在与上接触焊盘的第一表面相对的上接触焊盘的表面上。

公开(公告)号：US20140138806A1

公开(公告)日：2014-05-22

申请号：US14165707

申请日：2014-01-28

Applicant: General Electric Company

Inventor： Arun Virupaksha Gowda ,  Paul Alan McConnelee

IPC: H01L23/495 ,  H01L21/50

CPC classification number: H01L23/495 ,  H01L21/50 ,  H01L23/3735 ,  H01L23/49531 ,  H01L23/49575 ,  H01L23/49811 ,  H01L24/24 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/01029 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/15747 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure.

Abstract translation: 公开了一种结合了引线框连接的功率覆盖（POL）封装结构。 该POL结构包括具有电介质层的POL子模块，附着到电介质层的至少一个半导体器件，并且包括由半导体材料构成的衬底和形成在衬底上的多个连接焊盘，以及金属互连 结构电耦合到所述至少一个半导体器件的多个连接焊盘，金属互连结构延伸穿过通过介电层形成的通孔，以便连接到多个连接焊盘。 POL结构还包括电耦合到POL子模块的引线框架，引线框架包括被配置为与外部电路结构互连的引线。