-
公开(公告)号：US10096697B2
公开(公告)日：2018-10-09
申请号：US15874208
申请日：2018-01-18
摘要： A method comprises providing a structure defined by a silicon material on a buried oxide layer of a substrate; causing a nucleation of a III-V material in a sidewall of the structure defined by the silicon material; adjusting a growth condition to facilitate a first growth rate of the III-V material in directions along a surface of the sidewall and a second growth rate of the III-V material in a direction laterally from the surface of the sidewall, wherein the second growth rate is less than the first growth rate; and processing the silicon material and the III-V material to form a fin.
-
公开(公告)号：US10090562B2
公开(公告)日：2018-10-02
申请号：US15890686
申请日：2018-02-07
IPC分类号： H01M10/052 , H01M10/0585 , C23F4/00 , H01M10/04 , H01M10/0525
摘要： A method for forming a thin film lithium ion battery includes, under a same vacuum seal, forming a stack of layers on a substrate including an anode layer, an electrolyte, a cathode layer and a first cap over the stack of layers to protect the layers from air. Under a same vacuum seal, the stack of layers is etched with a non-reactive etch process in accordance with a hardmask, and a second cap layer is formed over the stack of layers without breaking the vacuum seal. Contacts coupled to the cathode and the anode are formed.
-
公开(公告)号：US10079249B2
公开(公告)日：2018-09-18
申请号：US15259096
申请日：2016-09-08
IPC分类号： H01L21/8234 , H01L27/12 , H01L29/78 , H01L29/66 , H01L29/10 , H01L21/033 , H01L27/02 , H01L21/84 , H01L27/088
CPC分类号： H01L27/1211 , H01L21/0337 , H01L21/823412 , H01L21/823431 , H01L21/823456 , H01L21/823462 , H01L21/845 , H01L27/0207 , H01L27/0886 , H01L29/1033 , H01L29/6656 , H01L29/66795 , H01L29/785
摘要： A method including patterning a continuous fin having a first segment and a second segment in a semiconductor layer, the first segment is arranged at an angle relative to the second segment, and forming a first gate and a second gate substantially parallel to each other, the first gate substantially covering sides and a top of a portion of the first segment of the continuous fin, the second gate substantially covering sides and a top of a portion of the second segment of the continuous fin.
-
公开(公告)号：US10032793B2
公开(公告)日：2018-07-24
申请号：US15267646
申请日：2016-09-16
发明人： Effendi Leobandung
IPC分类号： H01L27/088 , H01L27/12 , H01L21/84 , H01L21/306 , H01L21/8234 , H01L29/08 , H01L21/02 , H01L29/161 , H01L29/201 , H01L29/06 , H01L29/78 , H01L21/3105
摘要： A method for forming a semiconductor device. It includes forming fin structures on a substrate, where the fin structure defines source and drain regions. It also includes forming a gate stack in contact with the fin structure, depositing an insulator on the substrate, and applying an etching process to remove portions of the insulator to form a trench to the source region. It also includes implanting a damaged epitaxial material into the trench and to the source regions, and applying a second etching process to remove portions of the insulator to form a trench in the insulator to the drain regions. Finally, the method includes growing an epitaxial junction material over the source and drain regions, and depositing a metal over the substrate.
-
公开(公告)号：US10030265B2
公开(公告)日：2018-07-24
申请号：US14596284
申请日：2015-01-14
发明人： Effendi Leobandung
IPC分类号： C12Q1/68 , B01L3/00 , G01N27/414 , G01N33/487 , C12Q1/6869 , H01L21/266 , H01L21/311 , G01N27/447 , H01L21/762 , H01L29/786
摘要： Embodiments of the invention include a method for fabricating a semiconductor device, the resulting structure, and a method for using the resulting structure. A substrate is provided. A hard mask layer is patterned over at least a portion of the substrate. Regions of the substrate not protected by the hard mask are doped to form a source region and a drain region. The hard mask layer is removed. A dielectric layer is deposited on the substrate. An insulative layer is deposited on the dielectric layer. A nano-channel is created by etching a portion of the insulative layer which passes over the source region and the drain region.
-
公开(公告)号：US20180197946A1
公开(公告)日：2018-07-12
申请号：US15400351
申请日：2017-01-06
发明人： Effendi Leobandung
IPC分类号： H01L49/02 , H01L23/522
CPC分类号： H01L28/92 , H01L23/5223 , H01L28/75
摘要： An on-chip metal-insulator-metal (MIM) capacitor with enhanced capacitance is provided by forming the MIM capacitor along sidewall surfaces and a bottom surface of each trench of a plurality of trenches formed in a back-end-of-the-line (BEOL) metallization stack to increase a surface area of the MIM capacitor.
-
公开(公告)号：US20180166456A1
公开(公告)日：2018-06-14
申请号：US15882502
申请日：2018-01-29
发明人： Effendi Leobandung
IPC分类号： H01L27/11539 , H01L29/78 , H01L29/788 , H01L29/51 , H01L27/11536
摘要： After forming a first sacrificial gate stack over a portion of a first semiconductor fin located in a logic device region of a substrate, and a second sacrificial gate stack over a portion of a second semiconductor fin located in a memory device region of the substrate, in which each of the first sacrificial gate stack and the second sacrificial gate stack includes, from bottom to top, a tunneling oxide portion, a floating gate electrode, a control oxide portion, a gate conductor and a gate cap, an entirety of the first sacrificial gate stack is removed to provide a first gate cavity, and only the gate cap and the gate conductor are removed from the second sacrificial gate stack to provide a second gate cavity. Next, a high-k gate dielectric and a gate electrode are formed within each of the first gate cavity and the second gate cavity.
-
公开(公告)号：US20180158948A1
公开(公告)日：2018-06-07
申请号：US15874680
申请日：2018-01-18
发明人： Effendi Leobandung
IPC分类号： H01L29/78 , H01L29/66 , H01L29/423 , H01L21/02 , H01L29/06 , H01L21/306 , H01L29/08
CPC分类号： H01L29/7827 , B82Y10/00 , H01L21/02603 , H01L21/30604 , H01L21/823456 , H01L21/823487 , H01L27/088 , H01L29/0649 , H01L29/0676 , H01L29/0847 , H01L29/401 , H01L29/41741 , H01L29/42376 , H01L29/42392 , H01L29/66439 , H01L29/66469 , H01L29/66545 , H01L29/66666 , H01L29/78642 , H01L29/78681 , H01L29/78684 , H01L29/78696
摘要： A method of making a vertical field effect transistor includes forming a semiconductor nanowire that extends from a substrate surface. A first sacrificial layer is deposited over the substrate surface, and a second sacrificial layer is deposited over the first sacrificial layer such that each of the first and second sacrificial layers are formed peripheral to the nanowire. The second sacrificial layer is then patterned to form a dummy gate structure. Thereafter, the first sacrificial layer is removed and source and drain regions are deposited via epitaxy directly over respective portions of the nanowire.
-
公开(公告)号：US09985100B2
公开(公告)日：2018-05-29
申请号：US15497894
申请日：2017-04-26
IPC分类号： H01L21/338 , H01L29/10 , H01L21/8234 , H01L21/223 , H01L21/324 , H01L29/66 , H01L29/78 , H01L29/36 , H01L21/02 , H01L29/161 , H01L27/088
CPC分类号： H01L29/1083 , H01L21/02236 , H01L21/02381 , H01L21/02428 , H01L21/02532 , H01L21/2236 , H01L21/324 , H01L21/823431 , H01L21/823481 , H01L21/823493 , H01L27/0886 , H01L29/161 , H01L29/36 , H01L29/6653 , H01L29/6656 , H01L29/66803 , H01L29/7851
摘要： A method for doping punch through stoppers (PTSs) includes forming fins in a monocrystalline substrate, forming a dielectric layer at a base portion between the fins and forming spacers on sidewalls of the fins down to a top portion of the dielectric layer. The dielectric layer is recessed to form gaps between the top portion of the dielectric layer and the spacer to expose the fins in the gaps. The fins are doped through the gaps to form PTSs in the fins.
-
公开(公告)号：US09977185B2
公开(公告)日：2018-05-22
申请号：US15347046
申请日：2016-11-09
IPC分类号： G02B6/00 , G02B6/12 , G02B6/122 , G02B6/42 , H01L31/0216 , H01L31/103 , H01L31/18 , G02B6/132
CPC分类号： G02B6/12004 , G02B6/12002 , G02B6/122 , G02B6/132 , G02B6/4201 , G02B6/428 , G02B2006/12121 , G02B2006/12123 , G02B2006/12176 , H01L31/02161 , H01L31/1035 , H01L31/1828 , H01L31/184
摘要： An optoelectronic device includes an integrated circuit including electronic devices formed on a front side of a semiconductor substrate. A barrier layer is formed on a back side of the semiconductor substrate. A photonics layer is formed on the barrier layer. The photonics layer includes a core for transmission of light and a cladding layer encapsulating the core and including a different index of refraction than the core. The core is configured to couple light generated from a component of the optoelectronic device.
-
-
-
-
-
-
-
-
-
搜索结果
790 条记录 (耗时 0.028 秒)
