公开(公告)号：US20200027876A1

公开(公告)日：2020-01-23

申请号：US16440700

申请日：2019-06-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Shigeki KOYA ,  Yasunari UMEMOTO ,  Takayuki TSUTSUI

IPC: H01L27/082 ,  H01L21/8252 ,  H01L23/00 ,  H01L29/205 ,  H01L29/73 ,  H01L29/737 ,  H01L29/66 ,  H01L23/498

Abstract: A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.

公开(公告)号：US20190386122A1

公开(公告)日：2019-12-19

申请号：US16436674

申请日：2019-06-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Isao OBU ,  Kaoru IDENO ,  Shigeki KOYA

IPC: H01L29/737 ,  H01L29/417 ,  H01L29/423

Abstract: A collector layer, a base layer, and an emitter layer that are disposed on a substrate form a bipolar transistor. An emitter electrode is in ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in plan view. A difference in dimension with respect to a longitudinal direction of the emitter layer between the emitter layer and an ohmic contact interface at which the emitter layer and the emitter electrode are in ohmic contact with each other is larger than a difference in dimension with respect to a width direction of the emitter layer between the emitter layer and the ohmic contact interface.

公开(公告)号：US20190115457A1

公开(公告)日：2019-04-18

申请号：US16152285

申请日：2018-10-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Shigeki KOYA ,  Isao OBU

IPC: H01L29/737 ,  H01L29/205 ,  H01L29/08 ,  H01L29/10 ,  H01L21/285 ,  H01L21/308 ,  H01L21/306 ,  H01L29/66

Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.

公开(公告)号：US20180309417A1

公开(公告)日：2018-10-25

申请号：US15946552

申请日：2018-04-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Masahiro SHIBATA ,  Kenichi NAGURA

IPC: H03F1/52 ,  H01L23/00 ,  H01L29/06 ,  H01L29/04 ,  H03F3/213 ,  H01L29/737 ,  H01L27/02 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423 ,  H01L23/48 ,  H01L29/861 ,  H01L21/768 ,  H03F3/195 ,  H01L21/02 ,  H01L29/36 ,  H01L29/207 ,  H01L29/45 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311

CPC classification number: H03F1/52 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/0274 ,  H01L21/2654 ,  H01L21/28575 ,  H01L21/30612 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/76898 ,  H01L21/8252 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/85 ,  H01L25/16 ,  H01L27/0248 ,  H01L27/0605 ,  H01L27/0635 ,  H01L27/0652 ,  H01L27/0664 ,  H01L29/045 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/205 ,  H01L29/207 ,  H01L29/36 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/452 ,  H01L29/66204 ,  H01L29/66242 ,  H01L29/66318 ,  H01L29/7371 ,  H01L29/861 ,  H01L29/8613 ,  H01L2224/0221 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0362 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05084 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/0518 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/10329 ,  H01L2924/10337 ,  H01L2924/13051 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/19041 ,  H01L2924/19043 ,  H03F1/565 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/411 ,  H03F2200/426 ,  H03F2200/444 ,  H03F2200/451 ,  H01L2924/00

Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

公开(公告)号：US20180233475A1

公开(公告)日：2018-08-16

申请号：US15954420

申请日：2018-04-16

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari UMEMOTO ,  Daisuke TOKUDA ,  Tsunekazu SAIMEI ,  Hiroaki TOKUYA

IPC: H01L23/00 ,  H01L29/08 ,  H01L29/737 ,  H01L29/66 ,  H01L29/20 ,  H01L29/732 ,  H01L29/205 ,  H01L29/417

CPC classification number: H01L24/13 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L29/0692 ,  H01L29/0817 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/6631 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7375 ,  H01L29/7378 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13026 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13563 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/10329 ,  H01L2924/10337 ,  H01L2924/10338 ,  H01L2924/13051 ,  H01L2924/13055 ,  H01L2924/1423 ,  H01L2924/351 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

公开(公告)号：US20180097092A1

公开(公告)日：2018-04-05

申请号：US15820897

申请日：2017-11-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Shigeru YOSHIDA ,  Masahiro SHIBATA

IPC: H01L29/737 ,  H01L29/12 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/40

CPC classification number: H01L29/737 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/12 ,  H01L29/20 ,  H01L29/401 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/66318 ,  H01L29/7371

Abstract: An HBT includes a semiconductor substrate having first and second principal surfaces opposite each other; and a collector layer, a base layer, and an emitter layer stacked in this order on the first principal surface side of the semiconductor substrate. The collector layer includes a first semiconductor layer with metal particles dispersed therein, the metal particles each formed by a plurality of metal atoms bonded with each other.

公开(公告)号：US20180012979A1

公开(公告)日：2018-01-11

申请号：US15598456

申请日：2017-05-18

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari UMEMOTO ,  Shigeki KOYA ,  Shigeru YOSHIDA ,  Isao OBU

IPC: H01L29/737 ,  H01L29/08

CPC classification number: H01L29/7371 ,  H01L29/0817 ,  H01L29/158 ,  H01L29/66242 ,  H01L29/66318

Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, an emitter layer, and a semiconductor layer that are laminated in this order, wherein the emitter layer includes a first region having an upper surface on which the semiconductor layer is laminated, and a second region being adjacent to the first region and having an upper surface that is exposed, and the first and second regions of the emitter layer have higher doping concentrations in portions near the upper surfaces than in portions near an interface between the emitter layer and the base layer.

公开(公告)号：US20170077054A1

公开(公告)日：2017-03-16

申请号：US15361336

申请日：2016-11-25

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari UMEMOTO ,  Daisuke TOKUDA ,  Tsunekazu SAIMEI ,  Hiroaki TOKUYA

IPC: H01L23/00 ,  H01L29/20 ,  H01L29/205 ,  H01L29/737

CPC classification number: H01L24/13 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L29/0692 ,  H01L29/0817 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/6631 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7375 ,  H01L29/7378 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13026 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13563 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/10329 ,  H01L2924/10337 ,  H01L2924/10338 ,  H01L2924/13051 ,  H01L2924/13055 ,  H01L2924/1423 ,  H01L2924/351 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

Abstract translation: 一种包括双极晶体管的半导体器件，其中与发射极层电连接的柱凸起和第二布线彼此接触的第三开口在发射极层的纵向方向上偏离 第三开口直接位于发射极层上方的位置。 第三开口相对于发射极层布置成使得发射极层的纵向方向上的发射极层的端部和第三开口的开口的边缘基本上彼此对准。

公开(公告)号：US20160315060A1

公开(公告)日：2016-10-27

申请号：US15202749

申请日：2016-07-06

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari UMEMOTO ,  Daisuke TOKUDA ,  Tsunekazu SAIMEI ,  Hiroaki TOKUYA

IPC: H01L23/00 ,  H01L29/737

CPC classification number: H01L24/13 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L29/0692 ,  H01L29/0817 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/6631 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7375 ,  H01L29/7378 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13026 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13563 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/10329 ,  H01L2924/10337 ,  H01L2924/10338 ,  H01L2924/13051 ,  H01L2924/13055 ,  H01L2924/1423 ,  H01L2924/351 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

Abstract translation: 一种包括双极晶体管的半导体器件，其中与发射极层电连接的柱凸起和第二布线彼此接触的第三开口在发射极层的纵向方向上偏离 第三开口直接位于发射极层上方的位置。 第三开口相对于发射极层布置成使得发射极层的纵向方向上的发射极层的端部和第三开口的开口的边缘基本上彼此对准。

公开(公告)号：US20150349100A1

公开(公告)日：2015-12-03

申请号：US14821214

申请日：2015-08-07

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari UMEMOTO ,  Atsushi KUROKAWA ,  Tsunekazu SAIMEI

IPC: H01L29/732

CPC classification number: H01L29/7325 ,  H01L29/0821 ,  H01L29/152 ,  H01L29/20 ,  H01L29/7371

Abstract: P-type second semiconductor layers each interposed between a corresponding pair of n-type first semiconductor layers reduce the apparent doping concentration in the entire collector layer without reducing the doping concentrations in the first semiconductor layers. This improves the linearity of capacitance characteristics and enables sufficient mass productivity to be achieved. Interposing each of the second semiconductor layers between the corresponding pair of the first semiconductor layers reduce the average carrier concentration over the entire collector layer, which allows a wide depletion layer to be formed inside the collector layer and, as a result, reduces base-collector capacitance.

Abstract translation: 各自插入相应的一对n型第一半导体层之间的P型第二半导体层降低了整个集电极层中的表观掺杂浓度，而不降低第一半导体层中的掺杂浓度。 这提高了电容特性的线性，并且能够实现足够的批量生产率。 将相应的第一半导体层之间的每一个第二半导体层插入整个集电极层上的平均载流子浓度，这允许在集电极层内形成宽的耗尽层，结果减少了基极集电极 电容。