公开(公告)号：US10008488B2

公开(公告)日：2018-06-26

申请号：US15489031

申请日：2017-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkwan Lee ,  Kundae Yeom ,  Jongho Lee ,  Hogeon Song

IPC: H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/18 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16141 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00012

Abstract: In one embodiment, the semiconductor module includes a module substrate and a first substrate mounted on and electrically connected to a first surface of the module substrate. The first substrate has one or more first electrical connectors of the semiconductor module, and the first substrate electrically connecting the first electrical connector to the module substrate.

公开(公告)号：US20250167061A1

公开(公告)日：2025-05-22

申请号：US19029411

申请日：2025-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Park ,  Jongho Lee ,  Yeongkwon Ko ,  Teakhoon Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer to be spaced apart from each other, the semiconductor devices being electrically connected to the package substrate through the interposer, and a molding layer on the interposer covering the semiconductor devices and exposing upper surfaces of the semiconductor devices, the molding layer including at least one groove extending in one direction between the semiconductor devices, the groove having a predetermined depth from an upper surface of the molding layer.

公开(公告)号：US20240321666A1

公开(公告)日：2024-09-26

申请号：US18675881

申请日：2024-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Jongho Lee ,  Yeongkwon Ko

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L23/3157 ,  H01L21/568 ,  H01L23/293 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/1012 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/8185

Abstract: A method of manufacture for a semiconductor package includes; forming a molding member on side surfaces of the semiconductor chips, using an adhesive to attach a carrier substrate to upper surfaces of the molding member and the semiconductor chips, using a first blade having a first blade-width to cut away selected portions of the carrier substrate and portions of the adhesive underlying the selected portions of the carrier substrate, and using the first blade to partially cut into an upper surface of the molding member to form a first cutting groove, wherein the selected portions of the carrier substrate are dispose above portions of the molding member between adjacent ones of semiconductor chips, using a second blade having a second blade-width narrower than the first blade-width to cut through a lower surface of the molding member to form a second cutting groove, wherein a combination of the first cutting groove and the second cutting groove separate a package structure including a semiconductor chip supported by a cut portion of the carrier substrate and bonding the package structure to an upper surface of a package substrate.

公开(公告)号：US12062639B2

公开(公告)日：2024-08-13

申请号：US17529798

申请日：2021-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Jongho Lee ,  Yeongkwon Ko

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/4803 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/5385 ,  H01L23/562 ,  H01L24/16 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/73204

Abstract: A semiconductor package includes a lower substrate including a central region and an edge region, an upper substrate on the central region of the lower substrate, a first semiconductor chip on the upper substrate, a second semiconductor chip on the upper substrate and horizontally spaced apart from the first semiconductor chip, a reinforcing structure on the edge region of the lower substrate, and a molding layer that covers an inner sidewall of the reinforcing structure, a top surface of the lower substrate, a sidewall of the first semiconductor chip, a sidewall of the second semiconductor chip, and the upper substrate. The molding layer is interposed between the lower substrate and the upper substrate, between the upper substrate and the first semiconductor chip, and between the upper substrate and the second semiconductor chip. The first semiconductor chip is of a different type from the second semiconductor chip.

公开(公告)号：US20230260923A1

公开(公告)日：2023-08-17

申请号：US18307277

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho Kang ,  Un-Byoung Kang ,  Byeongchan Kim ,  Junyoung Park ,  Jongho Lee ,  Hyunsu Hwang

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L23/49822 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/16 ,  H01L23/3128 ,  H01L25/105 ,  H01L23/5383 ,  H01L2224/16225

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

公开(公告)号：US11728142B2

公开(公告)日：2023-08-15

申请号：US16883392

申请日：2020-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Jaeho Kwak ,  Boeun Jang ,  Seokyeon Hwang ,  Yongseok Seo ,  Sangsoo Kim ,  Seunghwan Kim ,  Jongho Park ,  Yongkwan Lee ,  Jongho Lee ,  Daewook Kim ,  Wonpil Lee ,  Changkyu Choi

IPC: H01J37/32 ,  C23C16/455 ,  C23C16/458 ,  H01L21/673

CPC classification number: H01J37/32449 ,  C23C16/45504 ,  C23C16/45589 ,  H01J37/32633 ,  C23C16/4583 ,  C23C16/45502 ,  C23C16/45591 ,  H01J37/32357 ,  H01L21/67326

Abstract: A surface treatment apparatus and a surface treatment system having the same are disclosed. The surface treatment apparatus includes a process chamber in which the surface treatment process is conducted, a plasma generator for generating process radicals as a plasma state for the surface treatment process, the plasma generator being positioned outside of the process chamber and connected to the process chamber by a supply duct, a heat exchanger arranged on the supply duct and cooling down temperature of the process radicals passing through the supply duct and a flow controller controlling the process radicals to flow out of the process chamber. The flow controller is connected to a discharge duct through which the process radicals are discharged outside the process chamber. The plasma surface treatment process is conducted to the package structure having minute mounting gap without the damages to the IC chip and the board.

公开(公告)号：US11682630B2

公开(公告)日：2023-06-20

申请号：US17349174

申请日：2021-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Gyuho Kang ,  Un-Byoung Kang ,  Byeongchan Kim ,  Junyoung Park ,  Jongho Lee ,  Hyunsu Hwang

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16225

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

公开(公告)号：US20230163088A1

公开(公告)日：2023-05-25

申请号：US18151622

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuekjae Lee ,  Jongho Lee ,  Jihoon Kim ,  Taehun Kim ,  Sangcheon Park ,  Jinkyeong Seol ,  Sanghoon Lee

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L24/06 ,  H01L25/0652 ,  H01L25/18 ,  H01L24/08 ,  H01L24/32 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0655 ,  H01L21/561 ,  H01L25/50 ,  H01L24/94 ,  H01L24/96 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/83099 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2224/32145 ,  H01L2224/08148 ,  H01L2224/08145 ,  H01L2224/05073 ,  H01L2224/05025 ,  H01L2224/05564 ,  H01L2224/05562 ,  H01L2224/08121 ,  H01L2224/06182 ,  H01L2224/13024 ,  H01L2224/08225 ,  H01L2224/32225 ,  H01L2224/92142 ,  H01L2224/8389 ,  H01L2224/80895

Abstract: A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

公开(公告)号：US11469156B2

公开(公告)日：2022-10-11

申请号：US17203084

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunki Kim ,  Sangsoo Kim ,  Seung Hwan Kim ,  Kyung Suk Oh ,  Yongkwan Lee ,  Jongho Lee

IPC: H01L23/433 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L25/07

Abstract: Disclosed is a semiconductor package comprising a package substrate, a first semiconductor chip on the package substrate and including a first region and a second region, a second semiconductor chip on the first region, a heat radiation spacer on the second region, a third semiconductor chip supported by the second semiconductor chip and the heat radiation spacer, and a molding layer covering the first to third semiconductor chips and the heat radiation spacer.

公开(公告)号：US11292732B2

公开(公告)日：2022-04-05

申请号：US16705745

申请日：2019-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho Lee ,  Kookjeong Seo ,  Hyesoon Yang ,  Jungsoo Lim

IPC: C02F1/44 ,  B01D61/02 ,  B01D61/12 ,  C02F1/00

Abstract: Disclosed is a water purifier. The water purifier includes a water quality sensor configured to measure quality of water that is suppled from a water supply source, a first filter configured to filter by a first method, a second filter configured to filter by a second method, a flow path shifting valve configured to selectively supply water that is supplied from the water supply source to the first filter or the second filter, and a processor configured to control the flow path shifting valve based on a water quality value that is measured by the sensor.