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    OPTICAL CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    51.
    发明申请
    OPTICAL CHIP PACKAGE AND METHOD FOR FORMING THE SAME 审中-公开

    公开(公告)号：US20200333542A1

    公开(公告)日：2020-10-22

    申请号：US16851099

    申请日：2020-04-17

    Applicant: XINTEC INC.

    Inventor： Jiun-Yen LAI ,  Yu-Ting HUANG ,  Hsing-Lung SHEN ,  Tsang-Yu LIU ,  Hui-Hsien WU

    IPC: G02B6/42

    Abstract: An optical chip package is provided. The optical chip package includes a first transparent substrate, a second transparent substrate, and a spacer layer. The first and second transparent substrates each has a first surface and a second surface opposite the first surface. The first transparent substrate has a thickness that is different than that of the second transparent substrate. The second transparent substrate is disposed over the first transparent substrate, and the spacer layer is bonded between the second surface of the first transparent substrate and the first surface of the second transparent substrate. The recess region extends from the second surface of the second transparent substrate into the first transparent substrate, so that the first transparent substrate has a step-shaped sidewall. A method of forming an optical chip package is also provided.

    SENSING CHIP PACKAGE AND A MANUFACTURING METHOD THEREOF
    54.
    发明申请
    SENSING CHIP PACKAGE AND A MANUFACTURING METHOD THEREOF 有权
    感应芯片包装及其制造方法

    公开(公告)号：US20170040372A1

    公开(公告)日：2017-02-09

    申请号：US15226327

    申请日：2016-08-02

    Applicant: XINTEC INC.

    Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Chia-Ming CHENG

    IPC: H01L27/146

    CPC classification number: H01L27/14636 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L27/14618 ,  H01L27/1464 ,  H01L27/14687 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014

    Abstract: This present invention provides a method of manufacturing a chip scale sensing chip package, comprising the steps of: providing a sensing device wafer having a first top surface and a first bottom surface opposite to each other, whereby the sensing device wafer comprises a plurality of chip areas, and each of the chip areas comprising a sensing device and a plurality of conductive pads adjacent to the sensing chip nearby the first top surface; providing a cap wafer having a second top surface and a second bottom surface opposite to each other, and bonding the second surface of the cap wafer to the first top surface of the sensing device wafer by sandwiching a first adhesive layer therebetween; providing a temporary carrier substrate, and bonding the temporary carrier substrate to the second top surface of the cap wafer by sandwiching a second adhesive layer therebetween; forming a wiring layer connecting to each of the conductive pads on the first bottom surface of the sensing device wafer; providing a first protective layer on the wiring layer; removing the temporary carrier substrate and the second adhesive layer; forming a second protective layer on the second top surface; removing the first protective layer; scribing the chip areas to generate a plurality of individual chip scale sensing chip package; and removing the second protective layer.

    Abstract translation: 本发明提供了一种制造芯片级感测芯片封装的方法，包括以下步骤：提供具有彼此相对的第一顶表面和第一底表面的感测装置晶片，由此感测装置晶片包括多个芯片 区域，并且每个芯片区域包括感测装置和与第一顶表面附近的感测芯片相邻的多个导电焊盘; 提供具有彼此相对的第二顶表面和第二底表面的盖晶片，并且通过在其间夹住第一粘合剂层将盖晶片的第二表面粘合到感测装置晶片的第一顶表面; 提供临时载体基板，并且通过在其间夹着第二粘合剂层将临时载体基板结合到盖晶片的第二顶表面; 形成连接到感测装置晶片的第一底表面上的每个导电焊盘的布线层; 在所述布线层上提供第一保护层; 去除所述临时载体基板和所述第二粘合剂层; 在所述第二顶表面上形成第二保护层; 去除第一保护层; 划片芯片区域以产生多个单独的芯片级感测芯片封装; 并移除第二保护层。

    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
    55.
    发明申请
    CHIP PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开
    芯片包装及其制造方法

    公开(公告)号：US20160355393A1

    公开(公告)日：2016-12-08

    申请号：US15171971

    申请日：2016-06-02

    Applicant: XINTEC INC.

    Inventor： Tsang-Yu LIU ,  Wei-Luen SUEN ,  Po-Han LEE

    IPC: B81B3/00 ,  B81C1/00

    CPC classification number: B81B3/0081 ,  B81B7/0077 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3677 ,  H01L23/481 ,  H01L2224/11

    Abstract: A chip package includes a chip having an upper surface and a lower surface. A sensing element is disposed on the upper surface of the chip, and a thermal dissipation layer is disposed below the lower surface of the chip. A plurality of thermal dissipation external connections are disposed below the thermal dissipation layer and in contact with the thermal dissipation layer.

    Abstract translation: 芯片封装包括具有上表面和下表面的芯片。 感测元件设置在芯片的上表面上，并且散热层设置在芯片的下表面下方。 多个散热外部连接设置在散热层下方并与散热层接触。

    MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE
    57.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE 有权
    半导体结构的制造方法

    公开(公告)号：US20150340403A1

    公开(公告)日：2015-11-26

    申请号：US14703796

    申请日：2015-05-04

    Applicant: XINTEC INC.

    Inventor： Yen-Shih HO ,  Shu-Ming CHANG ,  Yung-Tai TSAI ,  Tsang-Yu LIU

    IPC: H01L27/146 ,  H01L21/67 ,  H01L21/683

    CPC classification number: H01L27/14687 ,  H01L21/67092 ,  H01L21/6836 ,  H01L27/14685 ,  H01L31/18

    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A temporary bonding layer is used to adhere a carrier to a first surface of a wafer. A second surface of the wafer is adhered to an ultraviolet tape on a frame, and the temporary bonding layer and the carrier are removed. A protection tape is adhered to the first surface of the wafer. An ultraviolet light is used to irradiate the ultraviolet tape. A dicing tape is adhered to the protection tape and the frame, and the ultraviolet tape is removed. A first cutter is used to dice the wafer from the second surface of the wafer, such that plural chips and plural gaps between the chips are formed. A second cutter with a width smaller than the width of the first cutter is used to cut the protection tape along the gaps.

    Abstract translation: 半导体结构的制造方法包括以下步骤。 临时粘合层用于将载体粘附到晶片的第一表面。 将晶片的第二表面粘附到框架上的紫外线带上，并且移除临时粘合层和载体。 保护带粘附到晶片的第一表面。 使用紫外线照射紫外线带。 切割胶带粘附到保护带和框架上，并且除去紫外线带。 使用第一切割器从晶片的第二表面切割晶片，从而形成芯片之间的多个芯片和多个间隙。 使用宽度小于第一切割器的宽度的第二切割器沿着间隙切割保护带。

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