公开(公告)号：US20190148218A1

公开(公告)日：2019-05-16

申请号：US16228998

申请日：2018-12-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Georgios Vellianitis ,  Mark Van Dal ,  Blandine Duriez

IPC分类号： H01L21/762 ,  H01L29/78 ,  H01L29/165 ,  H01L29/205 ,  H01L29/06 ,  H01L21/764 ,  H01L29/66 ,  H01L29/10 ,  H01L21/306

CPC分类号： H01L21/76264 ,  H01L21/30604 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7853

摘要： A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer.

公开(公告)号：US20190097025A1

公开(公告)日：2019-03-28

申请号：US16148578

申请日：2018-10-01

申请人： MaxPower Semiconductor Inc.

发明人： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/739 ,  H01L29/423 ,  H01L29/40 ,  H01L29/417 ,  H01L29/16 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265 ,  H01L29/36 ,  H01L27/088 ,  H01L29/06

CPC分类号： H01L29/66734 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/36 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/7835

摘要： Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

公开(公告)号：US20190081142A1

公开(公告)日：2019-03-14

申请号：US16189858

申请日：2018-11-13

申请人： Infineon Technologies AG

发明人： Anton Mauder ,  Franz-Josef Niedernostheide ,  Christian Philipp Sandow

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/10 ,  H01L29/739 ,  H01L29/423 ,  H01L29/417 ,  H01L29/36

CPC分类号： H01L29/0696 ,  H01L29/0692 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7813

摘要： A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, first and second cells electrically connected to the first load terminal structure and to a drift region, the drift region having a first conductivity type; a first mesa in the first cell and including: a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region; a second mesa in the second cell and including: a port region of the opposite conductivity type and electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure. The insulation structure houses a control electrode structure, and a guidance electrode arranged between the mesas.

公开(公告)号：US20180366544A1

公开(公告)日：2018-12-20

申请号：US16100425

申请日：2018-08-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L27/12 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/10 ,  H01L29/08

CPC分类号： H01L29/0673 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827

摘要： Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.

公开(公告)号：US20180331213A1

公开(公告)日：2018-11-15

申请号：US15593651

申请日：2017-05-12

申请人： GLOBAL FOUNDRIES INC.

发明人： Steven Bentley ,  Puneet Harischandra Suvarna ,  Julien Frougier ,  Bartlomiej Jan Pawlak

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L29/7827 ,  H01L29/1033 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

摘要： A fin extends from, and is perpendicular to, a planar surface of a substrate. A self-aligned bottom source/drain conductor is on the substrate adjacent the fin, a bottom insulator spacer is on the bottom source/drain conductor adjacent the fin, and a gate insulator is on a channel portion of the fin. A gate conductor is on the gate insulator, a self-aligned top source/drain conductor contacts the channel portion of the fin distal to the bottom insulator spacer, a top gate length limit insulator is positioned where the channel portion meets the top source/drain conductor, and a bottom gate length limit insulator is positioned where the channel portion meets the bottom insulator spacer. The gate length of the gate conductor is defined by a distance between the gate length limit insulators.

公开(公告)号：US20180315618A1

公开(公告)日：2018-11-01

申请号：US15725625

申请日：2017-10-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Jie Huang ,  Syun-Ming Jang ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang ,  Shu-Yuan Ku ,  Tai-Chun Huang ,  Chunyao Wang ,  Tze-Liang Lee ,  Chi On Chui

IPC分类号： H01L21/3205 ,  H01L29/66 ,  H01L29/49 ,  H01L29/10 ,  H01L29/78 ,  H01L21/28

CPC分类号： H01L21/32053 ,  H01L21/28052 ,  H01L29/1033 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7856

摘要： A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.

公开(公告)号：US20180286986A1

公开(公告)日：2018-10-04

申请号：US15994303

申请日：2018-05-31

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Junichiro SAKATA ,  Takuya HIROHASHI ,  Hideyuki KISHIDA

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/417 ,  H01L29/24 ,  H01L29/10 ,  H01L29/08 ,  H01L27/12 ,  H01L21/02

CPC分类号： H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78693 ,  H01L29/78696

摘要： It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.

公开(公告)号：US20180277670A1

公开(公告)日：2018-09-27

申请号：US15988375

申请日：2018-05-24

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Qing Cao ,  Kangguo Cheng ,  Zhengwen Li ,  Fei Liu

IPC分类号： H01L29/76 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/10 ,  H01L29/165 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06

CPC分类号： H01L29/7613 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/127 ,  H01L29/165 ,  H01L29/4232 ,  H01L29/42372 ,  H01L29/66439

摘要： Semiconductor devices include a thin channel region formed on a buried insulator. A source and drain region is formed on the buried insulator, separated from the channel region by notches. A gate structure is formed on the thin channel region.

公开(公告)号：US20180277665A1

公开(公告)日：2018-09-27

申请号：US15590243

申请日：2017-05-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： I-Sheng CHEN ,  Cheng-Hsien WU ,  Chih-Chieh YEH

IPC分类号： H01L29/73 ,  H01L29/10 ,  H01L27/088 ,  H01L29/66

CPC分类号： H01L29/7311 ,  H01L21/28518 ,  H01L27/088 ,  H01L29/1033 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553

摘要： A semiconductor device includes a substrate, at least one first semiconductor layer, and at least one second semiconductor layer. The at least one first semiconductor layer is disposed on the substrate, and the at least one second semiconductor layer is disposed on the at least one first semiconductor layer. The at least one first semiconductor layer includes a first doping portion, a second doping portion, a channel, and a semiconductor film. The second doping portion is adjacent to the first doping portion. The channel is disposed between the first doping portion and the second doping portion, and disposed with the substrate in parallel. The semiconductor film is disposed around the channel.

公开(公告)号：US20180277540A1

公开(公告)日：2018-09-27

申请号：US15464436

申请日：2017-03-21

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Hemanth Jagannathan ,  Vijay Narayanan

IPC分类号： H01L27/092 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/423 ,  H01L21/28 ,  H01L29/161 ,  H01L29/49 ,  H01L27/11 ,  H01L29/10

CPC分类号： H01L27/0922 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/4966

摘要： A method of fabricating a semiconductor structure having multiple defined threshold voltages includes: forming multiple field-effect transistor (FET) devices in the semiconductor structure, each of the FET devices including a channel and a gate stack formed of one of at least two different work function metals, the gate stack being formed proximate the channel; and varying a bang-gap of the channel in each of at least a subset of the FET devices by controlling a percentage of one or more compositions of a material forming the channel; wherein a threshold voltage of each of the FET devices is configured as a function of a type of work function metal forming the gate stack and the percentage of one or more compositions of the material forming the channel.