公开(公告)号：US20170097904A1

公开(公告)日：2017-04-06

申请号：US15314316

申请日：2015-05-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel

IPC: G06F13/16 ,  G11C11/4093 ,  G11C11/408 ,  G06F13/40

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1042 ,  G11C11/4082 ,  G11C11/4093 ,  G11C2207/229

Abstract: A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.

公开(公告)号：US20170054549A1

公开(公告)日：2017-02-23

申请号：US15250685

申请日：2016-08-29

Applicant: Rambus Inc.

Inventor： Bret G. Stott ,  Craig E. Hampel ,  Frederick A. Ware

IPC: H04L7/033 ,  H04L1/20 ,  H04L7/00

CPC classification number: H04L7/0337 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/20 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254 ,  H03L7/0814 ,  H04L1/203 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0041

Abstract: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

Abstract translation: 公开了一种信令系统。 信令系统包括用于接收数据信号和选通信号的第一集成电路（IC）芯片。 第一IC包括在由选通信号指示的时间采样数据信号以产生相位误差信息的电路，以及从第一IC器件输出相位误差信息的电路。 该系统还包括信令链路和经由信令链路耦合到第一IC芯片的第二IC芯片，以将数据信号和选通信号输出到第一IC芯片。 第二IC芯片包括延迟电路，用于通过延迟第一时间间隔的非周期性定时信号和定时控制电路来产生选通信号，以从第一IC芯片接收相位误差信息，并根据相位误差调整第一时间间隔 信息。

公开(公告)号：US09459960B2

公开(公告)日：2016-10-04

申请号：US14830358

申请日：2015-08-19

Applicant: Rambus Inc.

Inventor： Ely K. Tsern ,  Mark A. Horowitz ,  Frederick A. Ware

IPC: G06F11/00 ,  G06F3/06 ,  G11C29/52 ,  G06F11/14 ,  G06F11/10 ,  G06F11/07 ,  H04L1/00 ,  H04L1/18 ,  H04L1/08 ,  G11C11/401 ,  G11C29/04

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/006 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G06F11/1402 ,  G06F11/141 ,  G06F11/1443 ,  G11C11/401 ,  G11C29/52 ,  G11C2029/0411 ,  H04L1/0057 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1809

Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

Abstract translation: 存储器系统包括具有至少一个信号线的链路和控制器。 所述控制器包括耦合到所述链路以发送第一数据的至少一个发射机，以及耦合到所述发射机的第一误差保护发生器。 第一错误保护发生器动态地将错误检测码添加到第一数据的至少一部分。 至少一个接收器耦合到链路以接收第二数据。 第一错误检测逻辑确定控制器接收到的第二数据是否包含至少一个错误，并且如果检测到错误则断言第一错误状况。 该系统包括具有耦合到链路以传输第二数据的至少一个存储器件发送器的存储器件。 耦合到存储器件发射器的第二误差保护发生器动态地将错误检测码添加到第二数据的至少一部分。

公开(公告)号：US09450614B2

公开(公告)日：2016-09-20

申请号：US14475619

申请日：2014-09-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Scott C. Best

IPC: H03M13/15 ,  H03M13/00 ,  G06F11/10 ,  H03M13/53

CPC classification number: G06F11/1048 ,  H03M13/1525 ,  H03M13/19 ,  H03M13/617

Abstract: A memory system includes a memory module that supports error detection and correction (EDC) in a manner that relieves a memory controller or processor of some or all of the computational burden associated with EDC. Individual EDC components perform EDC functions on subsets of the data, and share data between themselves using relatively short, fast interconnections.

Abstract translation: 存储器系统包括以能够缓解存储器控制器或处理器与EDC相关联的一些或全部计算负担的方式支持错误检测和校正（EDC）的存储器模块。 单独的EDC组件在数据子集上执行EDC功能，并使用相对较短，快速的互连在其间共享数据。

公开(公告)号：US20160253258A1

公开(公告)日：2016-09-01

申请号：US15050246

申请日：2016-02-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0253 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1009 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/60 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7211

Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.

Abstract translation: 存储器系统包括表现出与写入操作不对称的磨损机制的非易失性物理存储器，例如闪速存储器。 易失性存储器的相对较小的缓存减少了写入次数，并且磨损均衡存储器访问方法将写入均匀地分布在非易失性存储器上。

公开(公告)号：US09431063B2

公开(公告)日：2016-08-30

申请号：US14827831

申请日：2015-08-17

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Paul D. Franzon

IPC: G11C8/00 ,  G11C5/02 ,  G11C29/00 ,  H01L23/538 ,  G11C7/22 ,  G11C11/4076

CPC classification number: G11C5/02 ,  G11C7/22 ,  G11C11/4076 ,  G11C29/80 ,  G11C29/808 ,  G11C2213/71 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations. Redundant storage is provided including a first storage area dedicated to storing failure address information of failure address locations in the first or second integrated circuit memory chips. The redundant storage includes a second storage area dedicated to storing data corresponding to the failure address locations. Matching logic matches incoming data transfer addresses to the stored failure address information.

Abstract translation: 公开了一种堆叠存储器，其包括具有第一存储位置的第一集成电路存储器芯片和与第一集成电路存储器芯片堆叠关系地设置的第二集成电路存储器芯片。 第二集成电路存储器芯片具有第二存储位置。 提供了冗余存储器，其包括专用于存储第一或第二集成电路存储器芯片中的故障地址位置的故障地址信息的第一存储区域。 冗余存储器包括专用于存储对应于故障地址位置的数据的第二存储区域。 匹配逻辑将输入的数据传输地址与存储的故障地址信息进行匹配。

公开(公告)号：US20160196864A1

公开(公告)日：2016-07-07

申请号：US15070376

申请日：2016-03-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

IPC: G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F1/06 ,  G06F1/105 ,  G06F1/12 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G06F13/1684 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4086 ,  G11C5/063 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012

Abstract: A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

Abstract translation: 存储器控制器组件包括发射电路和调整电路。 发送电路使用定时信号发送时钟信号并将数据写入DRAM，由DRAM采样的写入数据。 调整电路调整写入数据和定时信号的发送定时，使得定时信号的边沿转换与DRAM处的时钟信号的边沿转换对齐。

公开(公告)号：US20160161552A1

公开(公告)日：2016-06-09

申请号：US14950138

申请日：2015-11-24

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G01R31/28 ,  G11C29/12 ,  G11C29/50 ,  G11C29/02

CPC classification number: G01R31/2882 ,  G01R31/2607 ,  G01R31/31726 ,  G11C29/022 ,  G11C29/12015 ,  G11C29/16 ,  G11C29/50012 ,  G11C2029/0401 ,  H03L7/00

Abstract: A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.

Abstract translation: 半导体IC器件包括用于传送定时信号的定时电路，所述定时电路被配置为接收第一测试信号并且响应于所述第一测试信号而在定时信号中产生延迟，所述第一测试信号包括第一定时 事件。 所述半导体IC器件还包括接口电路，其被配置为响应于所述定时信号传送所述数据信号，所述接口电路还被配置为接收第二测试信号并响应于所述第二测试信号而实现所述数据信号的延迟 所述第二测试信号包括根据测试标准与所述第一定时事件相关的第二定时事件。

公开(公告)号：US09350421B2

公开(公告)日：2016-05-24

申请号：US14072307

申请日：2013-11-05

Applicant: Rambus Inc.

Inventor： John W. Poulton ,  Frederick A. Ware ,  Carl W. Werner

IPC: H03K5/22 ,  H04B3/54 ,  G06F13/40 ,  H04B10/50 ,  H04B3/56 ,  H04L25/02 ,  H04B10/40 ,  H04B10/073

CPC classification number: H04B3/56 ,  G06F13/4072 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2924/15311 ,  H03F3/24 ,  H04B3/54 ,  H04B10/0731 ,  H04B10/40 ,  H04B10/50 ,  H04B2001/0408 ,  H04L25/0272 ,  H01L2924/00014

Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.

公开(公告)号：US20160118116A1

公开(公告)日：2016-04-28

申请号：US14987309

申请日：2016-01-04

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Gary Bela Bronner ,  Frederick A. Ware

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0097 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/75 ,  G11C2213/78 ,  G11C2213/79

Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.

Abstract translation: 存储单元包括第一电阻性存储器元件，在公共节点处与第一电阻式存储器元件电耦合的第二电阻存储元件，以及包括与公共节点电耦合的输入端的开关元件，该开关元件包括驱动器配置 在一个或多个操作期间浮动。