公开(公告)号：US20150294925A1

公开(公告)日：2015-10-15

申请号：US14656631

申请日：2015-03-12

申请人： ChipMOS Technologies Inc.

发明人： Chi-Jin SHIH

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L23/49503 ,  H01L21/4832 ,  H01L21/4842 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49541 ,  H01L24/09 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/04042 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/491 ,  H01L2224/49112 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/92247 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A quad flat no-lead package includes an encapsulant, and a plurality of chip pads, a plurality of bond pads and a chip disposed in the encapsulant. Each chip pad is connected to at least one of the chip pads adjacent thereto by a first extending portion. The chip pads and the bond pads are arranged in an array. The chip pads are disposed at the center of the array and the bond pads are disposed around the chip pads. Each of the bond pads and at least one of the bond pads or one of the chip pads adjacent thereto each has a second extending portion formed therebetween and corresponding to each other. Every two of the second extending portions corresponding to each other are separated by a groove. The chip is mounted on a top surface of the chip pads and is electrically coupled to the bond pads.

摘要翻译： 四边形无引线封装包括密封剂和多个芯片焊盘，多个焊盘和设置在密封剂中的芯片。 每个芯片焊盘通过第一延伸部连接到与其相邻的至少一个芯片焊盘。 芯片焊盘和接合焊盘被布置成阵列。 芯片焊盘设置在阵列的中心，并且接合焊盘设置在芯片焊盘周围。 每个接合焊盘和至少一个接合焊盘或与其相邻的芯片焊盘之一每个都具有形成在它们之间并相互对应的第二延伸部分。 彼此对应的每两个第二延伸部分被凹槽分开。 芯片安装在芯片焊盘的顶表面上，并且电耦合到焊盘。

公开(公告)号：US09159685B2

公开(公告)日：2015-10-13

申请号：US14494026

申请日：2014-09-23

申请人： CHIPMOS TECHNOLOGIES INC.

发明人： Geng-Shin Shen ,  Chung-Pang Chi

IPC分类号： H01L21/44 ,  H01L23/00

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/034 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/11831 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13022 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a semiconductor substrate, a pad, a passivation layer and a patterned insulating layer. The patterned insulating layer is disposed on the passivation layer and partially and directly covers the first opening of the pad to expose a second opening. The conductive structure comprises an under bump metal (UBM) layer and a conductive bump. The UBM layer is disposed in the second opening defined by the patterned insulating layer and is electrically connected to the pad. The conductive bump is disposed on the UBM layer and is electrically connected to the UBM layer. The upper surface of the conductive bump is greater than the upper surface of the patterned insulating layer, while the portion of the conductive bump disposed in the second opening is covered by the UBM layer.

摘要翻译： 提供了一种用于半导体芯片的导电结构和用于形成导电结构的方法。 半导体芯片包括半导体衬底，衬垫，钝化层和图案化绝缘层。 图案化的绝缘层设置在钝化层上，并且部分地并且直接覆盖焊盘的第一开口以露出第二开口。 导电结构包括凹凸金属（UBM）层和导电凸块。 UBM层设置在由图案化的绝缘层限定的第二开口中，并且电连接到焊盘。 导电凸块设置在UBM层上并与UBM层电连接。 导电凸块的上表面大于图案化绝缘层的上表面，而布置在第二开口中的导电凸块的部分被UBM层覆盖。

公开(公告)号：US20150279771A1

公开(公告)日：2015-10-01

申请号：US14642122

申请日：2015-03-09

申请人： ChipMOS Technologies Inc.

发明人： Chien-Chih HUANG

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/32235 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/8389 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/105 ,  H05K2203/0514 ,  H05K2203/056 ,  H01L2224/45099 ,  H01L2224/81 ,  H01L2221/68381 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package and manufacturing method thereof are disclosed. The semiconductor package includes a photosensitive conductive layer, a chip and an encapsulant. The photosensitive conductive layer includes at least one electrically conductive portion and at least one insulating portion. The chip is disposed on the photosensitive conduct layer and electrically coupled the least one electrically conductive portion. The encapsulant covers the chip and the photosensitive conductive layer.

摘要翻译： 公开了半导体封装及其制造方法。 半导体封装包括光敏导电层，芯片和密封剂。 光敏导电层包括至少一个导电部分和至少一个绝缘部分。 芯片设置在光敏导电层上并电耦合至少一个导电部分。 密封剂覆盖芯片和感光导电层。

公开(公告)号：US20150232325A1

公开(公告)日：2015-08-20

申请号：US14593352

申请日：2015-01-09

申请人： ChipMOS Technologies, Inc.

发明人： Shih-Wen CHOU

IPC分类号： B81B7/00 ,  B81C1/00

CPC分类号： B81B7/0061 ,  B81B2201/0257 ,  B81C2203/0136 ,  H01L24/45 ,  H01L2224/16245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4826 ,  H01L2224/73207 ,  H01L2924/15151 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： An MEMS package and the manufacturing method thereof are disclosed. The MEMS package includes a package substrate, a block ring, an MEMS chip and an encapsulating material. The package substrate has an inner surface, a corresponding outer surface and a signal opening that penetrates the inner surface and outer surface. The package substrate further has at least one inner contact pad and at least one outer contact pad wherein the outer contact pad is disposed on the outer surface. The inner contact pad is electrically coupled to the outer contact pad. The block ring is disposed on the inner surface and surrounds the signal opening. The MEMS chip has an active surface, at least one sensor device and at least one chip contact pad, wherein the sensor device and the chip contact pad are disposed on the active surface. The active surface is attached to the block ring so that the sensor device is surrounded by the block ring. The chip contact pad is electrically coupled to the inner contact pad. The encapsulating material covers the MEMS chip, the outer side of the block ring and the inner contact pad.

摘要翻译： 公开了一种MEMS封装及其制造方法。 MEMS封装包括封装衬底，块环，MEMS芯片和封装材料。 封装基板具有内表面，相应的外表面和穿透内表面和外表面的信号开口。 封装衬底还具有至少一个内部接触焊盘和至少一个外部接触焊盘，其中外部接触焊盘设置在外部表面上。 内接触垫电耦合到外接触垫。 块环设置在内表面上并围绕信号开口。 MEMS芯片具有活性表面，至少一个传感器装置和至少一个芯片接触垫，其中传感器装置和芯片接触垫设置在活性表面上。 活动表面附接到块环，使得传感器装置被块环包围。 芯片接触焊盘电耦合到内部接触焊盘。 封装材料覆盖MEMS芯片，块环的外侧和内部接触垫。

公开(公告)号：US09087912B2

公开(公告)日：2015-07-21

申请号：US14198493

申请日：2014-03-05

申请人： CHIPMOS TECHNOLOGIES INC

发明人： Tsung Jen Liao

IPC分类号： H01L23/48 ,  H01L23/00

CPC分类号： H01L24/81 ,  H01L21/561 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/10 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/1624 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/244 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/821 ,  H01L2224/83191 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00014

摘要： The present disclosure relates to a method for wafer level packaging and a package structure thereof. The method includes several steps. A through hole is formed in the interposer with a thickness that is less than the length of a first conducting pillar. The first conducting pillar is disposed inside the through hole. A redistribution layer is disposed and electrically connected with the first conducting pillar. A solder ball is disposed on the redistribution layer so as to form a wafer level packaging structure.

摘要翻译： 本公开涉及一种晶片级封装的方法及其封装结构。 该方法包括几个步骤。 在插入件中形成的通孔的厚度小于第一导电柱的长度。 第一导柱设置在通孔的内部。 再分配层设置并与第一导电柱电连接。 在再分配层上设置焊球，以形成晶片级封装结构。

公开(公告)号：US09082710B2

公开(公告)日：2015-07-14

申请号：US13849294

申请日：2013-03-22

申请人： ChipMOS Technologies, Inc.

发明人： Ying-Tai Tang

IPC分类号： H01L23/58 ,  H01L21/66 ,  H01L23/498

CPC分类号： H01L22/30 ,  H01L22/32 ,  H01L23/49838 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2924/00012

摘要： A chip packaging substrate includes a flexible substrate, a plurality of test pads, and a plurality of leads, wherein the flexible substrate has a first surface and a second surface, and the first surface has a user area and a test pad area configured thereon. The test pads are arranged in at least three rows within the test pad area. The lead connected to the test pad in the middle row includes a first section extending from the chip to the test pad area and a second section disposed on the second surface, wherein one end of the second section penetrates the flexible substrate to connect with the first section and the other end penetrates the flexible substrate to connect with the test pad, so as to increase the dimensions of the test pads.

摘要翻译： 芯片封装基板包括柔性基板，多个测试焊盘和多个引线，其中柔性基板具有第一表面和第二表面，并且第一表面具有配置在其上的用户区域和测试焊盘区域。 测试垫被布置在测试垫区域内至少三排。 连接到中间行的测试垫的引线包括从芯片延伸到测试焊盘区域的第一部分和设置在第二表面上的第二部分，其中第二部分的一端穿透柔性基板以与第一部分连接 并且另一端穿透柔性基板以与测试垫连接，以便增加测试垫的尺寸。

公开(公告)号：US20150162260A1

公开(公告)日：2015-06-11

申请号：US14304975

申请日：2014-06-15

申请人： ChipMOS Technologies Inc.

发明人： Tsung-Jen Liao

IPC分类号： H01L23/34 ,  H01L21/48 ,  H01L23/00 ,  H01L23/495

CPC分类号： H01L23/34 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/6836 ,  H01L23/13 ,  H01L23/142 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49568 ,  H01L24/48 ,  H01L24/82 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package structure including a leadframe, a chip, at least one heat dissipation pillar, and a molding compound is provided. The leadframe includes a die pad and a plurality of leads. The die pad has at least one through hole. The leads surround the die pad. The chip is located on the die pad and electronically connected to the leads. The chip includes an active surface and a back surface opposite to the active surface. The back surface of the chip is adhered to the die pad. The heat dissipation pillar is located on the back surface and passes through the through hole. The molding compound encapsulates the chip, at least parts of the leads, and the die pad. The molding compound includes at least one opening to expose the heat dissipation pillar. A manufacturing method of the chip package structure is also provided.

摘要翻译： 提供了包括引线框，芯片，至少一个散热柱和模塑料的芯片封装结构。 引线框架包括管芯焊盘和多个引线。 管芯焊盘至少有一个通孔。 引线围绕芯片焊盘。 芯片位于芯片焊盘上，并与引线电连接。 芯片包括有源表面和与有源表面相对的后表面。 芯片的背面粘附到芯片焊盘。 散热柱位于后表面，通过通孔。 模塑料封装芯片，引线的至少部分和芯片焊盘。 模塑料包括至少一个露出散热柱的开口。 还提供了芯片封装结构的制造方法。

公开(公告)号：US20150076670A1

公开(公告)日：2015-03-19

申请号：US14255973

申请日：2014-04-18

申请人： ChipMOS Technologies Inc.

发明人： Yu-Tang Pan ,  Shih-Wen Chou

IPC分类号： H01L23/31 ,  H01L23/373 ,  H01L21/56 ,  H01L23/00 ,  H01L23/552 ,  H01L23/433

CPC分类号： H01L23/552 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3737 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A chip package structure and a manufacturing method thereof are provided. The chip package structure includes a substrate, a chip, a plurality of wires, a film layer, a carrier, and an encapsulant. The substrate has an upper surface and a lower surface. The chip is mounted on the upper surface of the substrate. The wires are electrically connected to the chip and the substrate respectively. The film layer is attached to the substrate and entirely encapsulates the chip and the wires. The carrier is adhered on the film layer. The encapsulant is disposed on the upper surface of the substrate, wherein the encapsulant has an electro-magnetic shielding filler. The encapsulant at least partially encapsulates the carrier and the film layer, and the encapsulant covers the chip and the wires.

摘要翻译： 提供了芯片封装结构及其制造方法。 芯片封装结构包括基板，芯片，多根导线，薄膜层，载体和密封剂。 基板具有上表面和下表面。 芯片安装在基板的上表面上。 电线分别与芯片和基板电连接。 膜层附着在基片上，完全封装芯片和电线。 载体粘附在膜层上。 密封剂设置在基板的上表面上，其中密封剂具有电磁屏蔽填料。 密封剂至少部分地封装载体和膜层，并且密封剂覆盖芯片和电线。

公开(公告)号：US20150061121A1

公开(公告)日：2015-03-05

申请号：US14198493

申请日：2014-03-05

申请人： CHIPMOS TECHNOLOGIES INC

发明人： TSUNG JEN LIAO

IPC分类号： H01L23/00

CPC分类号： H01L24/81 ,  H01L21/561 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/10 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/1624 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/244 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/821 ,  H01L2224/83191 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00014

摘要： The present disclosure relates to a method for wafer level packaging and a package structure thereof. The method includes several steps. A through hole is formed in the interposer with a thickness that is less than the length of a first conducting pillar. The first conducting pillar is disposed inside the through hole. A redistribution layer is disposed and electrically connected with the first conducting pillar. A solder ball is disposed on the redistribution layer so as to form a wafer level packaging structure.

摘要翻译： 本公开涉及一种晶片级封装的方法及其封装结构。 该方法包括几个步骤。 在插入件中形成的通孔的厚度小于第一导电柱的长度。 第一导柱设置在通孔的内部。 再分配层设置并与第一导电柱电连接。 在再分配层上设置焊球，以形成晶片级封装结构。

公开(公告)号：US08786109B2

公开(公告)日：2014-07-22

申请号：US13793241

申请日：2013-03-11

申请人： Chipmos Technologies Inc.

发明人： Chung-Pang Chi

IPC分类号： H01L23/52 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768

CPC分类号： H01L23/49811 ,  H01L21/768 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/061 ,  H01L2224/06163 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13022 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/141 ,  H01L2224/14153 ,  H01L2924/381 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a plurality of first pads and second pads. The pad area is defined with a first area, a second area and a third area, wherein the first area is located between the second area and the third area. Each of the first pads and the second pads are interlaced to each other on the first area. The conductive structure comprises a plurality of conductive bumps formed on each of the first pads and the second pads respectively to electrically connect with each of the first pads and the second pads. Each of the conductive bumps has a first bump-width disposed on the first area and a second bump-width disposed on one of the second and third areas in which the first bump-width is shorter than the second bump-width.

摘要翻译： 提供了一种用于半导体芯片的导电结构和用于形成导电结构的方法。 半导体芯片包括多个第一焊盘和第二焊盘。 焊盘区域被限定有第一区域，第二区域和第三区域，其中第一区域位于第二区域和第三区域之间。 第一焊盘和第二焊盘中的每一个在第一区域上彼此交错。 导电结构包括分别形成在每个第一焊盘和第二焊盘上的多个导电凸块，以与第一焊盘和第二焊盘中的每一个电连接。 每个导电凸块具有设置在第一区域上的第一凸起宽度和设置在第一凸起宽度比第二凸起宽度短的第二和第三区域中的一个上的第二凸起宽度。