公开(公告)号：US09528185B2

公开(公告)日：2016-12-27

申请号：US14489398

申请日：2014-09-17

Applicant: Applied Materials, Inc.

Inventor： Sang Ki Nam ,  Tae Seung Cho ,  Ludovic Godet ,  Srinivas D. Nemani

IPC: H01L21/00 ,  C23C16/00 ,  C23C16/455 ,  H01J37/32 ,  C23C16/509 ,  C23C16/52

CPC classification number: C23C16/45565 ,  C23C16/5096 ,  C23C16/52 ,  H01J37/32082 ,  H01J37/32357 ,  H01J37/3244

Abstract: The present invention provides an apparatus having a plasma profile control plate disposed in a plasma processing chamber so as to locally alter plasma density to provide uniform plasma distribution across a substrate surface during processing. In one embodiment, a process kit includes a plate configured to be disposed in a plasma processing chamber, a plurality of apertures formed therethrough, the apertures configured to permit processing gases to flow through the plate, and an array of unit cells including at least one aperture formed in the plate, wherein each unit cell has an electrode assembly individually controllable relative to electrode assemblies disposed in at least two other unit cells.

Abstract translation: 本发明提供了一种装置，其具有设置在等离子体处理室中的等离子体轮廓控制板，从而局部地改变等离子体密度，以在处理期间在衬底表面上提供均匀的等离子体分布。 在一个实施例中，处理套件包括被配置为设置在等离子体处理室中的板，通过其形成的多个孔，所述孔被构造成允许处理气体流过板，以及包括至少一个 孔，其中每个单元电池具有相对于设置在至少两个其它单元电池中的电极组件可独立控制的电极组件。

公开(公告)号：US09515166B2

公开(公告)日：2016-12-06

申请号：US14276780

申请日：2014-05-13

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. Nemani ,  Ellie Y. Yieh ,  Ludovic Godet ,  Yin Fan

IPC: H01L21/469 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3115 ,  H01J37/32

CPC classification number: H01L21/02304 ,  H01J37/32357 ,  H01J37/32403 ,  H01J37/32422 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/31155 ,  H01L29/66795 ,  H01L29/66803

Abstract: Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer, and performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.

Abstract translation: 提供了使用用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠的选择性沉积工艺在翅片结构的不同位置形成所需材料的翅片结构的方法。 在一个实施方案中，在衬底上形成具有期望材料的结构的方法包括在形成在衬底上的结构的圆周上形成图案化的自组装单层，其中所述图案化的自组装单层包括在自身中形成的处理层 并且执行原子层沉积工艺，以从图案化的自组装单层形成主要在自组装单层上的材料层。

公开(公告)号：US09478433B1

公开(公告)日：2016-10-25

申请号：US14968500

申请日：2015-12-14

Applicant: Applied Materials, Inc.

Inventor： Qingjun Zhou ,  Jungmin Ko ,  Tom Choi ,  Sean Kang ,  Jeremiah Pender ,  Srinivas D. Nemani ,  Ying Zhang

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/31116 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31105 ,  H01L21/32136 ,  H01L21/32137

Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.

Abstract translation: 本文描述的实施例涉及用于图案化衬底的方法。 诸如双重图案化和四重图案化工艺的图案化工艺可以受益于本文所述的实施例，其包括对间隔材料执行惰性等离子体处理，对间隔材料的处理区域进行蚀刻工艺，并重复惰性等离子体处理 和蚀刻工艺以形成期望的间隔物轮廓。 惰性等离子体处理工艺可以是偏压工艺，并且蚀刻工艺可以是无偏的工艺。 可以控制各种加工参数，例如工艺气体比和压力，以影响所需的间隔物轮廓。

公开(公告)号：US20160240385A1

公开(公告)日：2016-08-18

申请号：US15000273

申请日：2016-01-19

Applicant: Applied Materials, Inc.

Inventor： Bhargav Citla ,  Chentsau Ying ,  Srinivas D. Nemani

IPC: H01L21/3065 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L21/02071 ,  H01L21/28035 ,  H01L21/32137

Abstract: The present disclosure provides methods for removing gate electrode residuals from a gate structure after a gate electrode patterning process. In one example, a method for forming high aspect ratio features in a gate electrode layer in a gate structure includes performing an surface treatment process on gate electrode residuals remaining on a gate structure disposed on a substrate, selectively forming a treated residual in the gate structure on the substrate with some untreated regions nearby in the gate structure, and performing a remote plasma residual removal process to remove the treated residual from the substrate.

Abstract translation: 本公开提供了在栅电极图案化工艺之后从栅极结构去除栅电极残留的方法。 在一个示例中，用于在栅极结构中的栅极电极层中形成高纵横比特征的方法包括对残留在设置在基板上的栅极结构上的栅电极残余物进行表面处理处理，在栅极结构中选择性地形成经处理的残留物 在衬底上具有栅极结构附近的一些未处理区域，以及执行远程等离子体残留去除工艺以从衬底去除经处理的残余物。

公开(公告)号：US09299577B2

公开(公告)日：2016-03-29

申请号：US14540577

申请日：2014-11-13

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Chia-Ling Kao ,  Sean Kang ,  Jeremiah T P Pender ,  Srinivas D. Nemani ,  Mehul B. Naik

IPC: H01L21/308 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/306

CPC classification number: H01L21/308 ,  H01J37/32357 ,  H01L21/02063 ,  H01L21/0234 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813

Abstract: Methods for eliminating early exposure of a conductive layer in a dual damascene structure and for etching a dielectric barrier layer in the dual damascene structure are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes patterning a substrate having a dielectric bulk insulating layer disposed on a dielectric barrier layer using a hardmask layer disposed on the dielectric bulk insulating layer as an etching mask, exposing a portion of the dielectric barrier layer after removing the dielectric bulk insulating layer uncovered by the dielectric bulk insulating layer, removing the hardmask layer from the substrate, and subsequently etching the dielectric barrier layer exposed by the dielectric bulk insulating layer.

Abstract translation: 提供了用于消除双镶嵌结构中的导电层的早期暴露并用于蚀刻双镶嵌结构中的介电阻挡层的方法。 在一个实施例中，用于蚀刻设置在衬底上的电介质阻挡层的方法包括使用设置在介电体绝缘层上的硬掩模层作为蚀刻掩模来图案化设置在电介质阻挡层上的介电体绝缘层的衬底， 在去除绝缘体绝缘层未覆盖的绝缘体绝缘层之后，从基板去除硬掩模层，随后蚀刻由绝缘体绝缘层暴露的电介质阻挡层的部分介电阻挡层。

公开(公告)号：US20160079034A1

公开(公告)日：2016-03-17

申请号：US14485505

申请日：2014-09-12

Applicant: Applied Materials Inc.

Inventor： Ellie Y. Yieh ,  Ludovic Godet ,  Jun Xue ,  Srinivas D. Nemani ,  DongQing (Karen) Li ,  Erica Chen

IPC: H01J37/317

CPC classification number: H01L21/26506 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/02323 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/31155 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: Species are supplied to a flowable layer over a substrate. A property of the flowable layer is modified by implanting the species to the flowable layer. The property comprises a density, a stress, a film shrinkage, an etch selectivity, or any combination thereof.

Abstract translation: 物质被提供到基底上的可流动层。 可流动层的性质通过将物种注入可流动层来改变。 该性质包括密度，应力，薄膜收缩率，蚀刻选择性或其任何组合。

公开(公告)号：US20160027655A1

公开(公告)日：2016-01-28

申请号：US14495794

申请日：2014-09-24

Applicant: Applied Materials, Inc.

Inventor： Hao Chen ,  Chentsau (Chris) Ying ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: H01L21/308 ,  H01L21/311 ,  H01L21/306 ,  C23C16/34 ,  H01L21/3065 ,  H01J37/32 ,  C23C16/455 ,  C23C16/50 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01L21/3086 ,  C23C16/04 ,  C23C16/34 ,  C23C16/345 ,  C23C16/45544 ,  C23C16/50 ,  H01J37/32009 ,  H01J37/32082 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/32139 ,  H01L21/67069 ,  H01L21/67207 ,  H01L21/67742

Abstract: A first portion of a multiple cycle spacer is formed on a sidewall of a patterned feature over a substrate. A spacer layer is deposited on the first portion using a first plasma process. The spacer layer is etched to form a second portion of the multiple cycle spacer on the first portion using a second plasma process. A cycle comprising depositing and etching of the spacer layer is continuously repeated until the multiple cycle spacer is formed.

公开(公告)号：US20150287612A1

公开(公告)日：2015-10-08

申请号：US14247035

申请日：2014-04-07

Applicant: Applied Materials, Inc.

Inventor： Olivier Luere ,  Sean S. Kang ,  Srinivas D. Nemani

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32139

Abstract: Embodiments of the present invention pertain to methods of forming more symmetric spacers which may be used for self-aligned multi-patterning processes. A conformal spacer layer of spacer material is formed over mandrels patterned near the optical resolution of a photolithography system using a high-resolution photomask. A carbon-containing layer is further formed over the conformal spacer layer. The carbon-containing layer is anisotropically etched to expose the high points of the conformal spacer layer while retaining carbon side panels. The conformal spacer layer may then be etched to form spacers without the traditional skewing of the profile towards one side or the other.

Abstract translation: 本发明的实施例涉及形成更多对称间隔物的方法，其可用于自对准多图案化工艺。 在使用高分辨率光掩模的光刻系统的光学分辨率附近形成的心轴上形成间隔物材料的保形间隔层。 在保形间隔层上进一步形成含碳层。 各向异性蚀刻含碳层以暴露保形间隔层的高点，同时保留碳侧面板。 然后可以蚀刻保形间隔层以形成间隔物，而不会使轮廓朝向一侧或另一侧的传统倾斜。

公开(公告)号：US09059398B2

公开(公告)日：2015-06-16

申请号：US13750892

申请日：2013-01-25

Applicant: Applied Materials, Inc.

Inventor： Jisoo Kim ,  Mang-Mang Ling ,  Khoi Doan ,  Chi Hong Ching ,  Srinivas D. Nemani

IPC: H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/16 ,  G11C11/161 ,  H01L27/222 ,  H01L43/08

Abstract: Embodiments of the invention provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in magnetoresistive random access memory applications. In one embodiment, a method of forming a MTJ structure on a substrate includes providing a substrate having a insulating tunneling layer disposed between a first and a second ferromagnetic layer disposed on the substrate, wherein the first ferromagnetic layer is disposed on the substrate followed by the insulating tunneling layer and the second ferromagnetic layer sequentially, supplying an ion implantation gas mixture to implant ions into the first ferromagnetic layer exposed by openings defined by the second ferromagnetic layer, and etching the implanted first ferromagnetic layer.

Abstract translation: 本发明的实施例提供了用于在磁阻随机存取存储器应用中在衬底上制造磁性隧道结（MTJ）结构的方法和装置。 在一个实施例中，在衬底上形成MTJ结构的方法包括提供衬底，其具有设置在设置在衬底上的第一和第二铁磁层之间的绝缘隧道层，其中第一铁磁层设置在衬底上， 绝缘隧道层和第二铁磁层，提供离子注入气体混合物以将离子注入到由第二铁磁层限定的开口暴露的第一铁磁层中，并蚀刻所注入的第一铁磁层。

公开(公告)号：US20150097276A1

公开(公告)日：2015-04-09

申请号：US14491828

申请日：2014-09-19

Applicant: Applied Materials, Inc.

Inventor： Jong Mun Kim ,  Kenny L. Doan ,  Li Ling ,  Jairaj Payyapilly ,  Srinivas D. Nemani ,  Daisuke Shimizu ,  Yuju Huang

IPC: H01L29/792 ,  H01L21/66 ,  H01L21/3065

CPC classification number: H01L29/66833 ,  H01L21/31116

Abstract: An article having alternating oxide layers and nitride layers is etched by an etch process. The etch process includes providing a first gas comprising C4F6H2 in a chamber of an etch reactor, ionizing the C4F6H2 containing gas to produce a plasma comprising a plurality of ions, and etching the article using the plurality of ions.

Abstract translation: 通过蚀刻工艺蚀刻具有交替的氧化物层和氮化物层的制品。 蚀刻工艺包括在蚀刻反应器的室中提供包含C 4 F 6 H 2的第一气体，使含有C 4 F 6 H 2的气体电离以产生包含多个离子的等离子体，并使用多个离子蚀刻该制品。