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公开(公告)号：US09973085B2
公开(公告)日：2018-05-15
申请号：US15218794
申请日：2016-07-25
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Jeanpierre Vicquery , Emilio Volpi
CPC classification number: H02M3/158 , H02M1/08 , H02M1/32 , H02M2001/0025
Abstract: A method and apparatus for controlling a converter are provided. In the method and apparatus, a converter is operated in accordance with a duty cycle and based on a difference between a feedback signal representing an output voltage of the converter and a reference signal. An overcurrent condition is detected in the converter. In response to detecting the overcurrent condition, the duty cycle used to operate the converter is limited and the reference signal is made to track the feedback signal to mitigate an output voltage overshoot at an end of the overcurrent condition.
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公开(公告)号：US09972394B2
公开(公告)日：2018-05-15
申请号：US15476003
申请日：2017-03-31
Applicant: STMicroelectronics S.r.l.
Inventor： Antonino Conte , Carmelo Paolino , Maurizio Francesco Perroni , Salvatore Polizzi
CPC classification number: G11C16/12 , G11C8/08 , G11C13/0004 , G11C16/08 , G11C16/20 , G11C16/26 , H03K3/356113 , H03K19/018521
Abstract: A level shifter circuit is designed to shift an input signal that switches within a first voltage range to supply an output signal that switches within a second voltage range, higher than the first voltage range. A first inverter stage has an input receiving the input signal and also has an output. A first capacitive element is connected between the output of the first input inverter stage and a first holding node. A latch stage is connected between the first holding node and a second holding node that is coupled to an output terminal, on which the output signal is present. The first input inverter stage is designed to operate in the first voltage range, and the latch stage is designed to operate in the second voltage range.
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693.发明申请公开(公告)号：US20180131342A1
公开(公告)日：2018-05-10
申请号：US15587579
申请日：2017-05-05
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Zamprogno , Maurizio Bongiorni , Pasquale Flora
CPC classification number: H03G3/30 , H02J7/0063 , H02J7/345 , H03F3/087 , H03F3/45475 , H03F3/45973 , H03F3/45977 , H03F2203/45021 , H03F2203/45114 , H03F2203/45116 , H03F2203/45212 , H03F2203/45288 , H03F2203/45528 , H03F2203/45536 , H04B10/6933
Abstract: A transimpedance amplifier circuit includes a feedback control loop that generates a compensation current at an input of a transimpedance amplifier. The feedback control loop includes a differential integrator with an integration capacitor. A time constant associated with charging the integration capacitor is variable as a function of a pre-charge control signal. During a pre-charge phase, the pre-charge control signal is set to a first value so as to set the time constant associated with charging the integration capacitor to a first time constant value. During an operation phase, the pre-charge control signal is set to a second value so as to increase the time constant associated with charging the integration capacitor to a second time constant value greater than the first time constant value for the pre-charge phase.
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公开(公告)号：US09966944B2
公开(公告)日：2018-05-08
申请号：US15216271
申请日：2016-07-21
Applicant: STMicroelectronics S.R.L.
Inventor： Sandro Rossi , Valeria Bottarel
IPC: H03K3/00 , H03K17/687 , H03K19/0175
CPC classification number: H03K17/687 , H03K3/3565 , H03K17/04123 , H03K17/063 , H03K17/6872 , H03K19/017509 , H03K19/018521 , H03K2217/0036 , H03K2217/0045
Abstract: A gate driver circuit for a half bridge or full bridge output driver stage having a high side branch connected to one or more high side transistors and a low side branch connected to one or more low side transistors. A high side gate driver and a low side gate driver receive input signals at a low voltage level and output signals at a high voltage level as gate driving signals for the high side transistors and low side transistors. Each of the high side and the low side branches of the gate driver includes a set-reset latch having a signal output that is fed as a gate signal to the corresponding transistor of the half bridge or full bridge driver. A differential capacitive level shifter circuit receives the input signals at a low voltage level and outputs high voltage signals to drive the set and reset inputs of the set-reset latch.
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695.发明申请公开(公告)号：US20180124521A1
公开(公告)日：2018-05-03
申请号：US15629518
申请日：2017-06-21
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Domenico GIUSTI , Sebastiano CONTI
IPC: H04R17/02 , B81C1/00 , B81B3/00 , H01L41/113 , H01L41/312 , H01L41/04 , H04R31/00
CPC classification number: H04R17/02 , B81B3/0037 , B81B2201/0235 , B81B2201/0257 , B81B2201/0264 , B81B2203/0127 , B81B2203/0315 , B81B2203/04 , B81B2207/012 , B81C1/00158 , G01L9/0042 , G01L9/0073 , H01L41/042 , H01L41/1132 , H01L41/1138 , H01L41/312 , H04R19/005 , H04R19/04 , H04R31/003 , H04R2201/003
Abstract: A MEMS sensor, in particular a microphone, of a piezoelectric type, formed in a membrane of semiconductor material accommodating a compliant portion, which extends from a first surface to a second surface of the membrane. The compliant portion has a Young's modulus lower than the rest of the membrane. A sensitive region having piezoelectric material extends on the first surface, over the compliant portion and is fixed at its ends to the membrane on opposite sides of the compliant portion. A third area of the membrane, arranged between the compliant portion and the second surface, forms a hinge element.
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Patent Agency Ranking
696.发明授权公开(公告)号：US09960692B2
公开(公告)日：2018-05-01
申请号：US15282459
申请日：2016-09-30
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Alberto Iorio , Maurizio Foresta
IPC: H02M3/335 , H02M1/08 , H03K3/012 , H03K17/687 , H02M7/217
CPC classification number: H02M3/33523 , H02M1/08 , H02M3/335 , H02M3/33592 , H03K3/012 , H03K17/163 , H03K17/687
Abstract: A driver includes a high-side driver transistor coupled between supply voltage and the gate drive nodes and provides a first charge current to a high side gate node of the high-side driver transistor until the gate drive node reaches a first gate drive threshold. Then a second charge current is provided to the high side gate node that is less than the first charge current. The gate drive node is limited to a first clamped threshold for a delay time. A gate drive current rise signal sets the value of the second charge current that charges the high side gate node and after the delay time the gate drive voltage is limited to a second clamped threshold greater than the first clamped threshold but less than the supply voltage. A gate drive programmable control signal sets the value of the second clamped threshold.
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697.发明授权公开(公告)号：US09960131B2
公开(公告)日：2018-05-01
申请号：US15251355
申请日：2016-08-30
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Paolo Colpani , Antonella Milani , Lucrezia Guarino , Andrea Paleari
CPC classification number: H01L24/05 , H01L23/3192 , H01L23/50 , H01L23/522 , H01L23/562 , H01L24/00 , H01L24/03 , H01L2224/02205 , H01L2224/02215 , H01L2224/04042 , H01L2224/05018 , H01L2224/05025 , H01L2224/05082 , H01L2224/05147 , H01L2224/05562 , H01L2224/05655 , H01L2924/04642 , H01L2924/05042 , H01L2924/351
Abstract: In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a dielectric layer. A via is provided through the passivation layer and the dielectric layer in the vicinity of the corners of the metallization. The via may be a “dummy” via without electrical connections to an active device and may be provided at a distance between approximately 1 micron (10−6 m.) and approximately 10 micron (10−5 m.) from each one of said converging sides landing on an underlying metal layer.
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公开(公告)号：US09959633B2
公开(公告)日：2018-05-01
申请号：US14675630
申请日：2015-03-31
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Angelo Bosco , Arcangelo Ranieri Bruna , Davide Giacalone , Rosetta Rizzo
CPC classification number: G06T7/44 , G06T5/002 , G06T5/20 , G06T2207/10004 , G06T2207/10024 , G06T2207/20021 , G06T2207/20182
Abstract: An embodiment relates to a method for the detection of texture of a digital image, including providing a raw data image of the image by means of Bayer image sensors, determining noise in at least a region of the raw data image and determining the texture based on the determined noise without using a high pass or low pass filter.
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公开(公告)号：US20180109290A1
公开(公告)日：2018-04-19
申请号：US15607256
申请日：2017-05-26
Applicant: STMicroelectronics S.r.l.
Inventor： Riccardo Fiorelli
CPC classification number: H04B3/56 , H01P1/10 , H03H7/004 , H04B2203/5404 , H04B2203/5483 , H04B2203/5491
Abstract: A coupling circuit for power line communications includes a coupling transformer having first and second mutually coupled windings, with the first winding connectable to a power line. The second winding includes a pair of intermediate taps with one or more tuning inductor therebetween. The inductor or inductors are set between a first portion and a second portion of the second winding of the coupling transformer. A switch member is provided coupled with the inductor. The switch member is selectively actuatable to short-circuit the inductor.
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700.发明申请公开(公告)号：US20180108767A1
公开(公告)日：2018-04-19
申请号：US15832680
申请日：2017-12-05
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Ferdinando Iucolano , Andrea Severino , Maria Concetta Nicotra , Alfonso Patti
IPC: H01L29/778 , H01L21/28 , H01L29/66 , H01L29/417 , H01L29/205 , H01L29/20 , H01L29/423
CPC classification number: H01L29/7784 , H01L21/0254 , H01L21/0262 , H01L21/28264 , H01L29/2003 , H01L29/205 , H01L29/41766 , H01L29/4236 , H01L29/66462 , H01L29/7783 , H01L29/7786
Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.
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