公开(公告)号：US07723828B2

公开(公告)日：2010-05-25

申请号：US12068613

申请日：2008-02-08

申请人： Wen-Jeng Fan ,  Yu-Mei Hsu

发明人： Wen-Jeng Fan ,  Yu-Mei Hsu

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A LOC leadframe-based semiconductor package includes a chip with multiple rows of bonding pads. At least a bus bar is attached to the chip and is disposed between a first row of bonding pads and the fingers of the leads. A plurality of bonding wires electrically connect the first row of bonding pads to the fingers of the leads. The portion of the bus bar attached to the active surface of the chip includes a bent section bent away from the fingers. A long bonding wire electrically connects one of a second row of bonding pads to one of the fingers of the leads by overpassing the bent section. Therefore, the distance between the long bonding wire and the bus bar is increased to avoid electrical short between the long bonding wire and the bus bar and to enhance the quality of electrical connections of the LOC semiconductor package.

摘要翻译： LOC引线框架半导体封装包括具有多排焊盘的芯片。 至少一个母线连接在芯片上，并且设置在第一排接合焊盘和引线的指状物之间。 多个接合线将第一排接合焊盘电连接到引线的指状物。 汇流条附接到芯片的有效表面的部分包括弯曲部分，该弯曲部分远离手指弯曲。 长接合线通过超过弯曲部分将第二排接合焊盘中的一个电线连接到引线的一个指状物。 因此，长接合线和母线之间的距离增加，以避免长接合线和母线之间的电短路并且提高LOC半导体封装的电连接的质量。

公开(公告)号：US07675186B2

公开(公告)日：2010-03-09

申请号：US11514349

申请日：2006-09-01

申请人： Cheng-Ping Chen ,  Wen-Jeng Fan

发明人： Cheng-Ping Chen ,  Wen-Jeng Fan

IPC分类号： H01L23/29

CPC分类号： H01L23/3128 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3135 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An IC package mainly includes a substrate having slot(s), a chip, a protective encapsulant, a stiffening encapsulant, and a plurality of external terminals. The Young's modulus of the stiffening encapsulant is greater than the one of the protective encapsulant and the curing shrinkage of the stiffening encapsulant is smaller than the one of the protective encapsulant. The protective encapsulant is formed on one of the surfaces of the substrate for encapsulating the chip. The stiffening encapsulant protrudes from the other surface of the substrate where the external terminals are disposed. Moreover, the stiffening encapsulant is formed inside the slot and is contacted with the chip. Since the stiffening encapsulant is embedded and formed inside the slot, therefore, the contact area of the stiffening encapsulant with the substrate is increased to enhance the warpage resistance of the IC package.

摘要翻译： IC封装主要包括具有槽的衬底，芯片，保护性密封剂，加强密封剂和多个外部端子。 加强密封剂的杨氏模量大于保护性密封剂中的一种，并且硬化密封剂的固化收缩率小于保护性密封剂中的一种。 保护性密封剂形成在用于封装芯片的衬底的一个表面上。 加强密封剂从设置有外部端子的基板的另一个表面突出。 此外，加强密封剂形成在槽内并与芯片接触。 由于加强型密封剂嵌入并形成在槽内，因此，加强密封剂与基板的接触面积增加，以提高IC封装的抗翘曲性。

公开(公告)号：US20090302443A1

公开(公告)日：2009-12-10

申请号：US12133898

申请日：2008-06-05

申请人： Chin-Fa Wang ,  Wan-Jung Hsieh ,  Yu-Mei Hsu

发明人： Chin-Fa Wang ,  Wan-Jung Hsieh ,  Yu-Mei Hsu

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L23/3107 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A leadframe-based semiconductor package and a leadframe for the package are revealed. The semiconductor package primarily includes parts of the leadframe including one or more first leads, one or more second leads, and a supporting bar disposed between the first leads and the second leads and further includes a chip attached to the first leads, the second leads and the supporting bar, a plurality of bonding wires and an encapsulant. The supporting bar has an extended portion projecting from the first bonding finger and the second bonding finger and connected to a non-lead side of the encapsulant wherein the extended portion has an arched bend to absorb the pulling stresses and to block stress transmission. Cracks caused by delamination of the supporting bar will not be created during trimming the supporting bar along the non-lead side of the encapsulant. Moisture penetration along the cracks of the supporting bar to the die- bonding plane under the chip is desirably prevented.

摘要翻译： 揭示了一种基于引线框架的半导体封装和封装的引线框架。 半导体封装主要包括引线框架的包括一个或多个第一引线，一个或多个第二引线和布置在第一引线和第二引线之间的支撑杆的部分，还包括附接到第一引线，第二引线和 支撑杆，多根接合线和密封剂。 支撑杆具有从第一接合指和第二接合指突起的延伸部分，并且连接到密封剂的非引线侧，其中延伸部具有拱形弯曲部以吸收拉应力并阻止应力传递。 在沿着密封剂的非引线侧修整支撑杆时不会产生由支撑杆分层引起的裂纹。 希望防止沿着支撑杆的裂纹向芯片下方的芯片接合平面的水分渗透。

公开(公告)号：US07605462B2

公开(公告)日：2009-10-20

申请号：US11709883

申请日：2007-02-23

申请人： Hung-Hsin Hsu ,  Chi-Chung Yu

发明人： Hung-Hsin Hsu ,  Chi-Chung Yu

IPC分类号： H01L23/48

CPC分类号： H01L23/5382 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K1/029 ,  H05K1/117 ,  H05K2201/10159 ,  H05K2201/10181 ,  H05K2203/175 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A universal substrate includes a plurality of inner pads and a plurality of outer pads. A plurality of bifurcate wirings and a plurality of fuses are formed on a surface of the substrate. The fuses are connected with the bifurcate wirings in series. By the bifurcate wirings and the fuses, each of the inner pads is electrically connected to all of the outer pads to provide optional electrical disconnections therebetween. Accordingly, the universal substrate can provide for various chips with different serial arrangements of bonding pads without replacing or manufacturing another kind of substrate.

摘要翻译： 通用基板包括多个内部焊盘和多个外部焊盘。 在基板的表面上形成多个分支布线和多个保险丝。 保险丝与串联的双叉线连接。 通过分支布线和熔丝，每个内焊盘电连接到所有的外焊盘，以在它们之间提供可选的电断开。 因此，通用基板可以提供具有不同的接合焊盘的串联布置的各种芯片，而不替换或制造另一种基板。

公开(公告)号：US20090224395A1

公开(公告)日：2009-09-10

申请号：US12042086

申请日：2008-03-04

申请人： Wen-Jeng FAN

发明人： Wen-Jeng FAN

IPC分类号： H01L23/48

CPC分类号： H01L23/49838 ,  H01L23/13 ,  H01L24/97 ,  H01L2924/01078 ,  H01L2924/01079

摘要： A substrate strip for semiconductor packages to slow the crack growth, primarily comprises a molding area and two side rails. The molding area includes a plurality of packaging units. The side rails are located outside the molding area and include two opposing longer sides of the substrate strip. A metal mesh is disposed on the side rails. The metal mesh consists of a plurality of crisscrossed wires having a plurality of isolated wire terminals at one edge of the metal mesh. Accordingly, crack growth is slowed by the specific metal mesh without damaging the packaging units. In one embodiment, the metal mesh is without boundary wires connecting to the isolated wire terminals to enhance the resistance to crack growth.

摘要翻译： 用于半导体封装的用于减缓裂纹扩展的衬底条主要包括模制区和两个侧轨。 成型区域包括多个包装单元。 侧轨位于模制区域的外侧，并且包括衬底条的两个相对的较长边。 金属网布置在侧轨上。 金属网由在金属网的一个边缘处具有多个隔离的导线端子的多个十字交叉的导线组成。 因此，特定金属网的裂纹扩展减慢，而不损害包装单元。 在一个实施例中，金属网没有连接到隔离导线端子的边界线，以增强对裂纹扩展的抵抗力。

公开(公告)号：US20090137069A1

公开(公告)日：2009-05-28

申请号：US11987235

申请日：2007-11-28

申请人： Li-Chih Fang ,  Wen-Jeng Fan

发明人： Li-Chih Fang ,  Wen-Jeng Fan

IPC分类号： H01L21/66

CPC分类号： H01L21/78 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00

摘要： A chip packaging process integrates a burn-in test or a high temperature test to simplify overall packaging and testing process flow. One or more chips are disposed on one or more units of a substrate strip where the substrate strip has a plurality of electrical open sections at the plating lines to electrically isolate the external pads between different units. After electrical connection and encapsulation, a burn-in test is executed at the same time of a post mold curing step, with a high-temperature testing if necessary. Therefore, the chips on the substrate strip has been gone through the burn-in test during the encapsulant is completely cured at the post mold curing step and the burn-in test is finished before the singulation step to reduce the overall testing time.

摘要翻译： 芯片封装过程集成了老化测试或高温测试，以简化整个封装和测试流程。 一个或多个芯片设置在衬底条的一个或多个单元上，其中衬底带在电镀线处具有多个电开路部分，以在不同单元之间电隔离外部焊盘。 在电连接和封装之后，在后模具固化步骤的同时进行老化测试，如果需要进行高温测试。 因此，在模塑固化步骤期间封装剂完全固化之前，衬底条上的芯片已经经过老化测试，并且在分离步骤之前完成老化测试以减少整体测试时间。

公开(公告)号：US20090039490A1

公开(公告)日：2009-02-12

申请号：US11889018

申请日：2007-08-08

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/12

CPC分类号： H01L23/49816 ,  H01L23/13 ,  H01L23/49838 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/09136 ,  H05K2201/094 ,  H05K2201/09736 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A mounting assembly of semiconductor packages is revealed, primarily comprising at least a semiconductor package having a plurality of external terminals, a package carrier, and solder paste. The solder paste joints the external terminals to the package carrier. According to the distance to a central line on a substrate of the semiconductor package, the external terminals are divided into at least two different groups. In one of the embodiment, different groups of the external terminals are bumps with non-equal heights to achieve a uniform standoff plane to compensate the warpage of the substrate. The predicted substrate warpage can be compensated without causing any soldering defects. In another embodiment, a plurality of compensating bumps are selectively disposed on one group of the external terminals with larger stacking gaps.

摘要翻译： 揭示了半导体封装的安装组件，主要包括至少具有多个外部端子的半导体封装，封装载体和焊膏。 焊膏将外部端子连接到封装载体。 根据与半导体封装的基板上的中心线的距离，将外部端子划分为至少两个不同的组。 在一个实施例中，不同组的外部端子是具有不相等高度的凸块，以实现均匀的支座平面以补偿基板的翘曲。 可以补偿预测的基板翘曲而不引起任何焊接缺陷。 在另一个实施例中，多个补偿凸块选择性地设置在具有较大堆积间隙的一组外部端子上。

公开(公告)号：US20080272489A1

公开(公告)日：2008-11-06

申请号：US11824448

申请日：2007-06-29

申请人： Li-Chih Fang ,  Ronald Iwata ,  Wen-Jeng Fan

发明人： Li-Chih Fang ,  Ronald Iwata ,  Wen-Jeng Fan

IPC分类号： H01L23/485

CPC分类号： H05K3/3452 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H05K2201/099 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor chip substrate with solder pad includes: a core layer and at least one conductive structure formed on the surface of the core layer; an insulation layer with at least one patterned opening covering the conductive structure, wherein the patterned opening has a center portion and a plurality of wing portions on the peripheral edge of the center portion to define the exposed area of the conductive structure as the solder pad. The solder pad with wing will improve the adhesion effect between the solder pad and the solder ball.

摘要翻译： 具有焊盘的半导体芯片基板包括芯层和形成在芯层表面上的至少一个导电结构; 绝缘层，其具有覆盖所述导电结构的至少一个图案化开口，其中所述图案化开口具有在所述中心部分的周边边缘上的中心部分和多个翼部，以限定所述导电结构的暴露区域作为所述焊盘。 具有机翼的焊盘将改善焊盘和焊球之间的粘附效应。

公开(公告)号：US20080116547A1

公开(公告)日：2008-05-22

申请号：US11600919

申请日：2006-11-17

申请人： Wen-Jeng Fan

发明人： Wen-Jeng Fan

IPC分类号： H01L23/495

CPC分类号： H01L23/16 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An IC package keeping the attachment level of leads on chip during molding process, mainly comprises a plurality of leads of a Lead-On-Chip (LOC) leadframe, a chip adhered under the leads, a plurality of bonding wires electrically connecting the chip to the leads, a plurality of first supporting columns disposed above some of the leads, a plurality of second supporting columns disposed under the some of the leads and a molding compound. The molding compound encapsulates the chip, the bonding wires, inner portions of the leads and sides of the first and second supporting columns. Therein, the first and second supporting columns are longitudinally corresponding to each other and adjacent the chip. The thickness including one of the first supporting columns, a corresponding one of the second supporting columns and one of the leads disposed corresponding to the selected first supporting column and the selected second supporting column is approximately as same as that of the molding compound. By means of the supporting columns in the package, it is able to prevent the problems of chip displacement during molding process and exposure of chip backside or the bonding wires.

摘要翻译： 一种在成型工艺中保持芯片引线附着水平的IC封装，主要包括芯片上引线框架（LOC）的多个引线，引线下方的芯片，将芯片电连接到 引线，设置在一些引线上方的多个第一支撑柱，设置在一些引线下方的多个第二支撑柱和模制化合物。 模塑料封装芯片，接合线，引线的内部和第一和第二支撑柱的侧面。 其中，第一和第二支撑柱纵向对应并且与芯片相邻。 包括第一支撑柱中的一个，相应的一个第二支撑柱和与所选择的第一支撑柱相对应设置的一个引线和所选择的第二支撑柱之间的厚度大致与模塑料的相同。 通过封装中的支撑柱，可以防止模制过程中芯片位移的问题和芯片背面或接合线的暴露。

公开(公告)号：US20080042255A1

公开(公告)日：2008-02-21

申请号：US11757601

申请日：2007-06-04

申请人： CHIN-TI CHEN

发明人： CHIN-TI CHEN

IPC分类号： H01L23/04 ,  H01L21/02

CPC分类号： H01L23/13 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/83051 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92147 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00015 ,  H01L2224/05599

摘要： A chip package structure and a fabrication method thereof are disclosed herein. The fabrication method includes: providing a substrate, wherein at least a through hole penetrates through the substrate; forming a block element surrounding the through hole of the substrate; forming an adhesive element surrounding the block element; disposing a chip on the substrate to cover the through hole, wherein the chip is fixed on the substrate with the adhesive element, wherein an active surface of the chip faces toward to the through hole and a portion of the active surface exposes to the through hole; electrically connecting the active surface of the chip to the lower surface of the substrate with a electrically-connecting element; and forming an encapsulant covering the abovementioned elements. Wherein the block element arranged around the through hole can avoid the overflow of the adhesive element, which may pollute those electrical contacts of the active surface of the chip, and restrict the stature of the adhesive element so as to reduce the probability of the particle pollution issue (for example the EMC filler), which may damage the active surface of the chip.

摘要翻译： 本文公开了一种芯片封装结构及其制造方法。 所述制造方法包括：提供衬底，其中至少一个通孔穿透所述衬底; 形成围绕所述基板的通孔的阻挡元件; 形成围绕所述块体元件的粘合元件; 在所述基板上设置芯片以覆盖所述通孔，其中所述芯片用所述粘合元件固定在所述基板上，其中所述芯片的有效表面朝向所述通孔，并且所述有源表面的一部分暴露于所述通孔 ; 用电连接元件将芯片的有源表面电连接到衬底的下表面; 并形成覆盖上述元件的密封剂。 其中布置在通孔周围的阻挡元件可以避免粘合元件的溢出，这可能污染芯片的有效表面的那些电触点，并且限制粘合元件的高度以便降低颗粒污染的可能性 （例如EMC填料），这可能会损坏芯片的有源表面。