公开(公告)号：US20050285250A1

公开(公告)日：2005-12-29

申请号：US11089361

申请日：2005-03-25

Applicant: Se-Young Jeong ,  Kang-Wook Lee

Inventor： Se-Young Jeong ,  Kang-Wook Lee

IPC: H01L23/12 ,  H01L23/02 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/11 ,  H01L2224/1146 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/81 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The chip package includes a first and second semiconductor chip. The first semiconductor chip has a first connection structure that electrically connects to a bond pad on a first surface of the first semiconductor chip. The second semiconductor chip has a second connection structure. The second connection structure is electrically connected to a bond pad on a first surface of the second semiconductor chip and extends through the second semiconductor chip to a second surface of the second semiconductor chip. A portion of the second connection structure extending to the second surface of the second semiconductor chip is electrically connected to the first connection structure and formed of a harder material than the first connection structure.

Abstract translation: 芯片封装包括第一和第二半导体芯片。 第一半导体芯片具有电连接到第一半导体芯片的第一表面上的接合焊盘的第一连接结构。 第二半导体芯片具有第二连接结构。 第二连接结构电连接到第二半导体芯片的第一表面上的接合焊盘，并且延伸穿过第二半导体芯片到第二半导体芯片的第二表面。 延伸到第二半导体芯片的第二表面的第二连接结构的一部分电连接到第一连接结构，并且由比第一连接结构更硬的材料形成。

公开(公告)号：US20050104181A1

公开(公告)日：2005-05-19

申请号：US10899175

申请日：2004-07-27

Applicant: Kang-Wook Lee ,  Se-Yong Oh ,  Young-Hee Song ,  Gu-Sung Kim

Inventor： Kang-Wook Lee ,  Se-Yong Oh ,  Young-Hee Song ,  Gu-Sung Kim

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/02

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A method of forming a wafer level stack structure, including forming a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, forming a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including at least one first device chip having a first plurality of input/output (I/O) pads and at least one second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.

公开(公告)号：US06890599B2

公开(公告)日：2005-05-10

申请号：US10461215

申请日：2003-06-13

Applicant: Stephen L. Buchwalter ,  Gareth Geoffrey Hougham ,  Kang-Wook Lee ,  John J. Ritsko ,  Mary Elizabeth Rothwell ,  Peter M. Fryer

Inventor： Stephen L. Buchwalter ,  Gareth Geoffrey Hougham ,  Kang-Wook Lee ,  John J. Ritsko ,  Mary Elizabeth Rothwell ,  Peter M. Fryer

IPC: G02F1/1343 ,  B05D1/32 ,  B05D3/00 ,  B05D5/00

CPC classification number: B82Y30/00 ,  G02F1/13439 ,  Y10T428/31663

Abstract: New etch barriers of indium-tin-oxide in the manufacturing process of thin film transistor-liquid crystal display are self-assembled monolayers, such as n-alkylsilanes. A typical process of applying a self-assembled monolayer is to ink a hydrolyzed n-octadecyltrimethoxysilane solution on to a stamp and then to transfer the solution onto ITO. The surface of the stamp may be polar enough to be wet with polar self-assembled monolayer solutions of an akylsilane. A non-polar stamp surface may be treated with oxygen plasma to obtain a wettable polar surface.

Abstract translation: 在薄膜晶体管 - 液晶显示器的制造过程中，铟锡氧化物的新的蚀刻屏障是自组装单层，例如正烷基硅烷。 施加自组装单层的典型方法是将水解的正十八烷基三甲氧基硅烷溶液油墨印刷到印模上，然后将溶液转移到ITO上。 印模的表面可以足够极性以使其与烷基硅烷的极性自组装单层溶液一起润湿。 可以用氧等离子体处理非极性印模表面以获得可润湿的极性表面。

公开(公告)号：US06784485B1

公开(公告)日：2004-08-31

申请号：US09502729

申请日：2000-02-11

Applicant: Stephan Alan Cohen ,  Timothy Joseph Dalton ,  John Anthony Fitzsimmons ,  Stephen McConnell Gates ,  Lynne M. Gignac ,  Paul Charles Jamison ,  Kang-Wook Lee ,  Sampath Purushothaman ,  Darryl D. Restaino ,  Eva Simonyi ,  Horatio Seymour Wildman

Inventor： Stephan Alan Cohen ,  Timothy Joseph Dalton ,  John Anthony Fitzsimmons ,  Stephen McConnell Gates ,  Lynne M. Gignac ,  Paul Charles Jamison ,  Kang-Wook Lee ,  Sampath Purushothaman ,  Darryl D. Restaino ,  Eva Simonyi ,  Horatio Seymour Wildman

IPC: H01L29792

CPC classification number: H01L21/76832 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76834 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device containing a diffusion barrier layer is provided. The semiconductor device includes at least a semiconductor substrate containing conductive metal elements; and, a diffusion barrier layer applied to at least a portion of the substrate in contact with the conductive metal elements, the diffusion barrier layer having an upper surface and a lower surface and a central portion, and being formed from silicon, carbon, nitrogen and hydrogen with the nitrogen being non-uniformly distributed throughout the diffusion barrier layer. Thus, the nitrogen is more concentrated near the lower and upper surfaces of the diffusion barrier layer as compared to the central portion of the diffusion barrier layer. Methods for making the semiconductor devices are also provided.

Abstract translation: 提供了包含扩散阻挡层的半导体器件。 半导体器件至少包括含有导电金属元素的半导体衬底; 以及扩散阻挡层，其被施加到与所述导电金属元件接触的所述基板的至少一部分，所述扩散阻挡层具有上表面，下表面和中心部分，并且由硅，碳，氮和 氢与氮在整个扩散阻挡层中不均匀地分布。 因此，与扩散阻挡层的中心部分相比，氮在扩散阻挡层的下表面和上表面附近更集中。 还提供了制造半导体器件的方法。

公开(公告)号：US06455443B1

公开(公告)日：2002-09-24

申请号：US09789422

申请日：2001-02-21

Applicant: Andrew Robert Eckert ,  John C. Hay ,  Jeffrey Curtis Hedrick ,  Kang-Wook Lee ,  Eric Gerhard Liniger ,  Eva Erika Simonyi

Inventor： Andrew Robert Eckert ,  John C. Hay ,  Jeffrey Curtis Hedrick ,  Kang-Wook Lee ,  Eric Gerhard Liniger ,  Eva Erika Simonyi

IPC: H01L2131

CPC classification number: H01L21/02282 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3124 ,  H01L21/76829

Abstract: A substantially defect-free, low-k dielectric film having improved adhesion is provided by (a) applying a silane coupling agent containing at least one polymerizable group to a surface of a substrate so as to provide a substantially uniform coating of said silane-coupling agent on said substrate; (b) heating the substrate containing the coating of the silane-coupling agent at a temperature of about 90° C. or above so as to provide a surface containing Si—O bonds; (c) rinsing the heated substrate with a suitable solvent that is effective in removing any residual silane-coupling agent; and (d) applying a dielectric material to the rinsed surface containing the Si—O bonds.

公开(公告)号：US5660921A

公开(公告)日：1997-08-26

申请号：US447350

申请日：1995-05-23

Applicant: Kie Yeung Ahn ,  James Lupton Hedrick, Jr. ,  Jeffrey William Labadie ,  Kang-Wook Lee ,  Robert James Twieg ,  Alfred Viehbeck ,  George Frederick Walker

Inventor： Kie Yeung Ahn ,  James Lupton Hedrick, Jr. ,  Jeffrey William Labadie ,  Kang-Wook Lee ,  Robert James Twieg ,  Alfred Viehbeck ,  George Frederick Walker

IPC: C08G73/18 ,  C08L71/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L23/532 ,  H05K1/00 ,  H05K1/03 ,  B32B15/00 ,  B32B15/08

CPC classification number: H01L23/5329 ,  C08G73/18 ,  C08L71/00 ,  H01L23/293 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/0346 ,  H05K3/4676 ,  Y10S428/901 ,  Y10T29/49155 ,  Y10T29/49171 ,  Y10T428/24917 ,  Y10T428/31605 ,  Y10T428/31721

Abstract: A multilevel electronic package comprising at least two levels, each level including a poly(aryl ether benzimidazole), a polymide and copper. A process of preparing this package is disclosed. Several novel poly(aryl ether benzimidazoles) useful in preparing this package are also set forth.

Abstract translation: 包括至少两个级别的多级电子封装，每个级别包括聚（芳基醚苯并咪唑），聚酰亚胺和铜。 公开了制备该包装的过程。 还介绍了可用于制备该包装的几种新颖的聚（芳基醚苯并咪唑）。

公开(公告)号：US5569739A

公开(公告)日：1996-10-29

申请号：US197941

申请日：1994-02-17

Applicant: Eleftherios Adamopoulos ,  Kang-Wook Lee ,  Terrence R. O'Toole ,  Sampath Purushothaman ,  Jane M. Shaw ,  Alfred Viehbeck ,  George F. Walker

Inventor： Eleftherios Adamopoulos ,  Kang-Wook Lee ,  Terrence R. O'Toole ,  Sampath Purushothaman ,  Jane M. Shaw ,  Alfred Viehbeck ,  George F. Walker

IPC: B32B7/10 ,  B32B15/08 ,  B32B15/088 ,  B32B27/00 ,  C08G73/00 ,  C08G73/10 ,  H01B3/30 ,  H01L21/52 ,  H05K1/03 ,  H05K3/46 ,  C08F8/34

CPC classification number: C08G73/1089 ,  C08G73/1003 ,  C08G73/1007 ,  C08G73/101 ,  H01B3/306 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/31721

Abstract: The disclosure describes a multilayer article of manufacture comprising a substrate having adhered to it a terminally unsaturated adhesive polyimide, where the surface of the adhesive opposite the substrate is adhered to a polyimide, the article further characterized in having one set or a plurality of alternating layers of the terminally unsaturated adhesive polyimide and the polyimide. the bonding operation.A novel adhesive polyimide is also described which is an adhesive polyimide such as ODPA-APB terminated with unsaturated heterocyclic monoamines such as azaadenines, aminobenzotriazoles, aminopurines or aminopyrazolopyrimidines and optionally anhydrides, aminoacetylenes, vinylamines or amino phosphines. The novel polyimide may also contain unsaturated heterocyclic groups in the polymer backbone or chain, either as a partial or complete replacement for the aromatic diamines used in synthesizing the polyimide. This novel adhesive polyimide in this invention acts as an adhesive layer for the polymer-substrate (copper, polymer, glass ceramic) interface as well as a copper diffusion barrier layer for the polymer copper interface.

Abstract translation: 本公开描述了一种多层制品，其包括粘附到其上的末端不饱和粘合聚酰亚胺的基底，其中与基底相对的粘合剂的表面粘附到聚酰亚胺上，该制品进一步的特征在于具有一组或多个交替层 的末端不饱和粘合聚酰亚胺和聚酰亚胺。 接合操作。 还描述了一种新型粘合聚酰亚胺，其是粘合聚酰亚胺，例如用不饱和杂环单胺如氮杂腺嘌呤，氨基苯并三唑，氨基嘌呤或氨基吡唑并嘧啶和任选的酸酐，氨基乙炔，乙烯胺或氨基膦封端的ODPA-APB。 新型聚酰亚胺还可以在聚合物主链或链中含有不饱和杂环基团，作为用于合成聚酰亚胺的芳族二胺的部分或完全替代物。 本发明中的这种新型粘合聚酰亚胺作为聚合物基材（铜，聚合物，玻璃陶瓷）界面的粘合剂层以及用于聚合物铜界面的铜扩散阻挡层。

公开(公告)号：US5516874A

公开(公告)日：1996-05-14

申请号：US319392

申请日：1994-10-06

Applicant: Kie Y. Ahn ,  James L. Hedrick, Jr. ,  Jeffrey W. Labadie ,  Kang-Wook Lee ,  Robert J. Twieg ,  Alfred Viehbeck ,  George F. Walker

Inventor： Kie Y. Ahn ,  James L. Hedrick, Jr. ,  Jeffrey W. Labadie ,  Kang-Wook Lee ,  Robert J. Twieg ,  Alfred Viehbeck ,  George F. Walker

IPC: C08G73/18 ,  C08L71/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L23/532 ,  H05K1/00 ,  H05K1/03 ,  C08G8/02 ,  C08G65/00

CPC classification number: H01L23/5329 ,  C08G73/18 ,  C08L71/00 ,  H01L23/293 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/0346 ,  H05K3/4676 ,  Y10S428/901 ,  Y10T29/49155 ,  Y10T29/49171 ,  Y10T428/24917 ,  Y10T428/31605 ,  Y10T428/31721

Abstract: A multilevel electronic package comprising at least two levels, each level including a poly(aryl ether benzimidazole), a polymide and copper. A process of preparing this package is disclosed. Several novel poly(aryl ether benzimidazoles) useful in preparing this package are also set forth.

Abstract translation: 包括至少两个级别的多级电子封装，每个级别包括聚（芳基醚苯并咪唑），聚酰亚胺和铜。 公开了制备该包装的过程。 还介绍了可用于制备该包装的几种新颖的聚（芳基醚苯并咪唑）。

公开(公告)号：US09808874B2

公开(公告)日：2017-11-07

申请号：US13613000

申请日：2012-09-13

Applicant: Kang-Wook Lee ,  Jae-Woong Nah ,  Nathalie Normand ,  Valerie Oberson

Inventor： Kang-Wook Lee ,  Jae-Woong Nah ,  Nathalie Normand ,  Valerie Oberson

IPC: B23K1/00 ,  B23K35/36 ,  B23K35/362

CPC classification number: B23K1/0016 ,  B23K35/3601 ,  B23K35/362

Abstract: The present invention is directed to a soldering method for joining objects is also provided, comprising the steps of applying a flux composition to at least a portion of one or more of the objects, and joining the objects.

公开(公告)号：US09181947B2

公开(公告)日：2015-11-10

申请号：US13387465

申请日：2009-12-02

Applicant: Kang-Wook Lee ,  Jin-Ung Shin ,  Geun-Hyung Lee ,  Seoung-Min Kang

Inventor： Kang-Wook Lee ,  Jin-Ung Shin ,  Geun-Hyung Lee ,  Seoung-Min Kang

IPC: F04C18/356 ,  F04C18/32 ,  F01C21/02 ,  F04C23/00 ,  F04C29/00 ,  F04C29/02 ,  F04C23/02

CPC classification number: F04C18/3564 ,  F01C21/02 ,  F04C18/322 ,  F04C23/008 ,  F04C23/02 ,  F04C29/0071 ,  F04C29/0085 ,  F04C29/023 ,  F04C2230/603 ,  F04C2240/10 ,  F04C2240/30 ,  F04C2240/40 ,  F04C2240/52 ,  F04C2240/60 ,  F04C2270/12

Abstract: A compressor is provided in which a rotary member suspended on a stationary member is rotated to compress a refrigerant. As the rotary member is suspended on a first stationary member and rotatably supported on a second stationary member spaced apart from the first stationary member, components can be easily centered and assembled with structural stability. In addition, oil stored in a hermetic container is supplied to a lubrication passage provided between the rotary member and the stationary member. This reduces friction loss between the components and achieves operational reliability. Moreover, the oil is easily introduced into a vane mounting hole in which a vane is linearly reciprocated. This reduces friction and abrasion of the vane and improves the operational reliability.

Abstract translation: 提供了一种压缩机，其中悬挂在固定构件上的旋转构件旋转以压缩制冷剂。 由于旋转构件悬挂在第一静止构件上并且可旋转地支撑在与第一固定构件间隔开的第二固定构件上，因此可以容易地将组件置于中心位置并且具有结构稳定性。 此外，存储在密封容器中的油被供给到设置在旋转构件和固定构件之间的润滑通道。 这减少了部件之间的摩擦损失并实现了操作可靠性。 此外，油容易地引入到叶片线性往复运动的叶片安装孔中。 这减少了叶片的摩擦和磨损，提高了操作的可靠性。