公开(公告)号：US20140159248A1

公开(公告)日：2014-06-12

申请号：US13709723

申请日：2012-12-10

Applicant: INVENSAS CORPORATION

Inventor： Ilyas Mohammed ,  Belgacem Haba

IPC: H01L23/48

CPC classification number: H01L25/0652 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/5389 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A microelectronic assembly can include a first package comprising a processor and a second package electrically connected to the first package. The second package can include two or more microelectronic elements each having memory storage array function and contacts at a respective element face, upper and lower opposite package faces, upper and lower terminals at the respective upper and lower package faces, and electrically conductive structure extending through the second package. At least portions of edges of respective microelectronic elements of the two or more microelectronic elements can be spaced apart from one another, so as to define a central region between the edges that does not overlie any of the element faces of the microelectronic elements of the second package. The electrically conductive structure can be aligned with the central region and can electrically connect the lower terminals with at least one of: the upper terminals or the contacts.

Abstract translation: 微电子组件可以包括包括处理器的第一封装和电连接到第一封装的第二封装。 第二封装可以包括两个或更多个微电子元件，每个微电子元件具有存储器阵列功能，并且在相应的元件面，上下相对的封装面，相应的上封装面和下封装面的上端和下端接触，并且导电结构延伸穿过 第二包。 两个或更多个微电子元件的相应微电子元件的边缘的至少部分可以彼此间隔开，以便限定边缘之间的中心区域，该中心区域不覆盖第二个微电子元件的微电子元件的元件面中的任一个 包。 导电结构可以与中心区域对准，并且可以将下端子与上端子或触点中的至少一个电连接。

公开(公告)号：US20140036454A1

公开(公告)日：2014-02-06

申请号：US13795756

申请日：2013-03-12

Applicant: INVENSAS CORPORATION

Inventor： Terrence Caskey ,  Ilyas Mohammed ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Michael Newman ,  Pezhman Monadgemi ,  Reynaldo Co ,  Ellis Chau ,  Belgacem Haba

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H01L25/105 ,  H01L21/486 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/02379 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H05K1/0298 ,  H05K3/46 ,  Y10T29/49126 ,  Y10T29/49162 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.

Abstract translation: 制造插入件的方法包括形成结合到第一元件的一个或多个第一表面的多个引线键合。 形成电介质封装，其接触将引线接合部彼此分隔开的引线接合的边缘表面。 进一步的处理包括去除第一元件的至少一部分，其中插入件具有通过至少封装相互隔开的第一和第二相对侧，并且插入件分别在第一和第二相对侧具有第一接触和第二接触， 分别与第一和第二部件电连接，第一触点通过引线键与第二触点电连接。

公开(公告)号：US20210225811A1

公开(公告)日：2021-07-22

申请号：US17217749

申请日：2021-03-30

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Javier A. Delacruz

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/78

Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.

公开(公告)号：US20210181511A1

公开(公告)日：2021-06-17

申请号：US17182016

申请日：2021-02-22

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Gabriel Z. Guevara ,  Min Tao

IPC: G02B27/01

Abstract: Apparatus and method relating generally to electronics are disclosed. In one such an apparatus, a film assembly has an upper surface and a lower surface opposite the upper surface. A dielectric film of the film assembly has a structured profile along the upper surface or the lower surface for having alternating ridges and grooves in a corrugated section in an at rest state of the film assembly. Conductive traces of the film assembly conform to the upper surface or the lower surface in or on the dielectric film in the corrugated section.

公开(公告)号：US20200321275A1

公开(公告)日：2020-10-08

申请号：US16837948

申请日：2020-04-01

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Stephen Morein ,  Ilyas Mohammed ,  Rajesh Katkar ,  Javier A. Delacruz

IPC: H01L23/50 ,  H01L23/367 ,  H01L23/49 ,  H01L23/64 ,  H01L21/48

Abstract: Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.

公开(公告)号：US20190273016A1

公开(公告)日：2019-09-05

申请号：US16136776

申请日：2018-09-20

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Gabriel Z. Guevara ,  Min Tao

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/302

Abstract: Apparatus and method relating generally to electronics are disclosed. In one such an apparatus, a film assembly has an upper surface and a lower surface opposite the upper surface. A dielectric film of the film assembly has a structured profile along the upper surface or the lower surface for having alternating ridges and grooves in a corrugated section in an at rest state of the film assembly. Conductive traces of the film assembly conform to the upper surface or the lower surface in or on the dielectric film in the corrugated section.

公开(公告)号：US10297582B2

公开(公告)日：2019-05-21

申请号：US14952064

申请日：2015-11-25

Applicant: Invensas Corporation

Inventor： Terrence Caskey ,  Ilyas Mohammed ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Michael Newman ,  Pezhman Monadgemi ,  Reynaldo Co ,  Ellis Chau ,  Belgacem Haba

IPC: H01L25/10 ,  H05K1/02 ,  H05K3/46 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.

公开(公告)号：US20190096803A1

公开(公告)日：2019-03-28

申请号：US16202392

申请日：2018-11-28

Applicant: Invensas Corporation

Inventor： Ilyas Mohammed

IPC: H01L23/522 ,  H01L23/00 ,  H05K3/40 ,  H01L23/538 ,  H01L21/768 ,  H01L21/56 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76877 ,  H01L21/76892 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/46 ,  H01L24/49 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45101 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45565 ,  H01L2224/45624 ,  H01L2224/45655 ,  H01L2224/45664 ,  H01L2224/45669 ,  H01L2224/4569 ,  H01L2224/48 ,  H01L2224/49 ,  H01L2224/73267 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01049 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/182 ,  H01L2924/191 ,  H01L2924/19107 ,  H05K3/4046 ,  H05K2201/10287 ,  H05K2203/1461 ,  H01L2924/00 ,  H01L2924/014

Abstract: A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are unconvered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer.

公开(公告)号：US10159148B2

公开(公告)日：2018-12-18

申请号：US15700483

申请日：2017-09-11

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H05K1/09 ,  H05K1/03 ,  H05K1/11 ,  H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H05K3/40 ,  H05K3/42 ,  H01L23/373 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

公开(公告)号：US20180295718A1

公开(公告)日：2018-10-11

申请号：US16007410

申请日：2018-06-13

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Craig Mitchell ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H05K1/02 ,  H01L23/498 ,  H01R12/71 ,  H05K3/42 ,  H05K1/11

CPC classification number: H05K1/0271 ,  H01L23/49827 ,  H01L2924/0002 ,  H01R12/714 ,  H05K1/114 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09645 ,  H05K2201/10378 ,  H05K2203/0242 ,  H05K2203/025 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for making an interconnection component includes forming a mask layer that covers a first opening in a sheet-like element that includes a first opening extending between the first and second surfaces of the element. The element consists essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. The first opening includes a central opening and a plurality of peripheral openings open to the central opening that extends in an axial direction of the central opening. A conductive seed layer can cover an interior surface of the first opening. The method further includes forming a first mask opening in at least a portion of the mask layer overlying the first opening to expose portions of the conductive seed layer within the peripheral openings; and forming electrical conductors on exposed portions of the conductive seed layer.