公开(公告)号：US5919546A

公开(公告)日：1999-07-06

申请号：US871419

申请日：1997-06-09

申请人： Michio Horiuchi ,  Yukiharu Takeuchi

发明人： Michio Horiuchi ,  Yukiharu Takeuchi

IPC分类号： H01L23/498 ,  H05K1/03 ,  H05K3/40 ,  B32B3/20

CPC分类号： H01L23/49827 ,  H05K3/4038 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01012 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0306 ,  H05K2201/0116 ,  H05K2201/10287 ,  H05K2203/0235 ,  H05K2203/1147 ,  Y10S428/901 ,  Y10T29/49211 ,  Y10T29/49215 ,  Y10T428/24273 ,  Y10T428/24851 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/249956 ,  Y10T428/249969 ,  Y10T428/249986 ,  Y10T428/249987

摘要： A wiring body, used for manufacturing a substrate, includes a columnar body, having an axis, made of fired porous inorganic insulator impregnated with an organic insulator; and a large number of metallic fine wires embedded in the columnar body in parallel with the axis while the metallic fine wires are arranged at intervals, wherein a ratio of the inorganic insulator in the columnar body is 50 to 80 volume %, preferably 50 to 60 volume %. A method for manufacturing a wiring body includes the steps of charging a dispersed solution, in which inorganic insulating powder is dispersed, into a container in which a number of metallic fine wires are arranged in parallel with the axis, drying the dispersed solution, and firing inorganic insulating powder so that the porosity of the fired body can be in a range from 20 to 50 volume % so as to form a columnar body; and the steps of impregnating the obtained porous columnar body with uncured organic insulating material, and curing the organic insulating material.

摘要翻译： 用于制造基板的布线体包括具有轴线的柱状体，其由浸渍有机绝缘体的烧制多孔无机绝缘体制成; 以及与该轴线平行嵌入柱状体中的大量金属细线，同时金属细线间隔配置，柱状体中的无机绝缘体的比例为50〜80体积％，优选为50〜60 体积％。 制造布线体的方法包括以下步骤：将分散有无机绝缘粉末的分散溶液装入其中多个金属细线与轴平行布置的容器中，干燥分散溶液并进行烧制 无机绝缘粉末，使得烧制体的孔隙率可以在20〜50体积％的范围内，形成柱状体; 以及用未固化的有机绝缘材料浸渍所获得的多孔柱状体并使有机绝缘材料固化的步骤。

公开(公告)号：US5294576A

公开(公告)日：1994-03-15

申请号：US990375

申请日：1992-12-15

申请人： Kihou Mizushima ,  Michio Horiuchi

发明人： Kihou Mizushima ,  Michio Horiuchi

IPC分类号： C04B35/185 ,  C04B35/19

CPC分类号： C04B35/185

摘要： A mullite ceramic composition comprises mullite powder as a raw material; at least one of a rare earth element compound and an alkaline earth element compound; and at least one of a Group 6B vanadium compound, niobium compound and a tantalum compound, and the mixture is fired.

摘要翻译： 莫来石陶瓷组合物包含莫来石粉为原料; 至少一种稀土元素化合物和碱土金属元素化合物; 和6B族钒化合物，铌化合物和钽化合物中的至少一种，并将该混合物烧制。

公开(公告)号：US08134444B2

公开(公告)日：2012-03-13

申请号：US12895915

申请日：2010-10-01

申请人： Michio Horiuchi ,  Yukio Shimizu ,  Kazunari Sekigawa ,  Tsuyoshi Kobayashi

发明人： Michio Horiuchi ,  Yukio Shimizu ,  Kazunari Sekigawa ,  Tsuyoshi Kobayashi

IPC分类号： H01F17/04 ,  H01R4/58

CPC分类号： H01F17/0013 ,  H01F41/041 ,  H01F2017/002 ,  Y10T29/4902

摘要： An inductor includes a core substrate including minute column-like electrical conductors extending between a front surface and a back surface of the core substrate. Each column-like electrical conductor is insulated from adjacent column-like electrical conductors by being surrounded by an insulating material. Insulation layers are formed on the front surface and the back surface of the core substrate, respectively. At least two connection electrical conductors extend through each of the insulation layers. Each connection electrical conductor is electrically connected to a plurality of the column-like electrical conductors. Wirings are formed on each of the insulation layers to connect said connection electrical conductors to each other electrically. The wirings, the connection electrical conductors and the column-like electrical conductors are connected to form a coil in a three-dimensional manner.

摘要翻译： 电感器包括芯基板，其包括在芯基板的前表面和后表面之间延伸的微小列状电导体。 每个柱状电导体被绝缘材料包围，与相邻的柱状电导体绝缘。 绝缘层分别形成在芯基板的前表面和后表面上。 至少两个连接电导体延伸穿过每个绝缘层。 每个连接电导体电连接到多个柱状电导体。 在每个绝缘层上形成布线，以将所述连接电导体彼此电连接。 连线，连接电导体和列状电导体被连接以形成三维方式的线圈。

公开(公告)号：US07264899B2

公开(公告)日：2007-09-04

申请号：US10642342

申请日：2003-08-18

申请人： Michio Horiuchi ,  Shigeaki Suganuma ,  Misa Watanabe ,  Shuji Yamazaki

发明人： Michio Horiuchi ,  Shigeaki Suganuma ,  Misa Watanabe ,  Shuji Yamazaki

IPC分类号： H01M2/14 ,  H01M8/10

CPC分类号： H01M8/1213 ,  H01M8/04089 ,  H01M8/124 ,  H01M8/2425 ,  H01M8/243 ,  Y02P70/56

摘要： A fuel cell comprised of a solid electrolyte layer sandwiched by a cathode layer and an anode layer to which a mixed gas of a fuel gas and air mixed together is supplied, wherein the fuel cell is formed into a spiral member comprised of a single cell layer comprised of the cathode layer, solid electrolyte layer, and anode layer stacked together or a multilayer member of a plurality of the single cell layers stacked together rolled up spirally, the cathode layer and anode layer forming facing surfaces of each upper stratum and lower stratum of the single cell layer or multilayer member adjoining each other in a diametrical direction of the spiral member are arranged through an electrical insulator, and the cathode layer and anode layer or the electrical insulator are or is formed with a gas passage enabling passage of the mixed gas, whereby it is possible to prevent an increase in size of the cell even if increasing the contact area of the anode layer and cathode layer with the air or fuel gas.

摘要翻译： 一种由阴极层夹持的固体电解质层和混合在一起的燃料气体和空气的混合气体的阳极层构成的燃料电池，其特征在于，所述燃料电池形成为由单电池层 由阴极层，固体电解质层和堆叠在一起的阳极层或堆叠在一起的多个单个电池层的多层构件螺旋地卷起，阴极层和阳极层形成每个上层和下层的相对表面 在螺旋构件的直径方向上彼此邻接的单电池层或多层构件通过电绝缘体布置，并且阴极层和阳极层或电绝缘体形成有能够使混合气体通过的气体通道 ，由此即使增加阳极层和阴极层与空气或f的接触面积，也可以防止电池尺寸的增加 uel气

公开(公告)号：US06404214B1

公开(公告)日：2002-06-11

申请号：US09468060

申请日：1999-12-20

申请人： Shigetsugu Muramatsu ,  Michio Horiuchi ,  Takuya Kazama

发明人： Shigetsugu Muramatsu ,  Michio Horiuchi ,  Takuya Kazama

IPC分类号： G01R3102

CPC分类号： H05K1/112 ,  G01R31/2886 ,  H01L2224/16237 ,  H05K1/0393 ,  H05K3/06 ,  H05K3/325 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10734

摘要： A substrate for inspecting an electronic device used for an electrical test of the electronic device having bump-shaped connection terminals, comprises: opening sections, the diameter of each opening being determined so that a connection terminal can be inserted into and drawn out from the opening, are formed penetrating the insulating substrate in a region on one side of an insulating substrate on which the electronic device is mounted, corresponding to an arrangement of the connection terminals; and wiring patterns, each of which is composed of a pad section being exposed onto a bottom face of the opening so that the pad can come into contact with the connection terminal so as to accomplish electrical continuity, a connecting pad section formed in a region outside of the region in which the pad section is formed, which comes into contact with a contact terminal of an inspection device so as to accomplish electrical continuity, and a wiring section for electrically connecting the pad section with the connecting pad section, are formed on the other side of the insulating substrate.

摘要翻译： 一种用于检查用于具有凸起形连接端子的电子设备的电气测试的电子设备的基板，包括：开口部分，每个开口的直径被确定为使得连接端子能够从开口插入和拉出 对应于连接端子的布置，在安装有电子设备的绝缘基板的一侧的区域中穿过绝缘基板; 以及布线图案，每个布线图案由暴露于开口的底面的焊盘部分组成，使得焊盘能够与连接端子接触以实现电连续性;连接焊盘部分形成在外部区域 形成有与检查装置的接触端子接触以实现电连续性的形成有焊盘部的区域，以及用于将焊盘部与连接焊盘部电连接的布线部，形成在 绝缘基板的另一侧。

公开(公告)号：US06297553B1

公开(公告)日：2001-10-02

申请号：US09422746

申请日：1999-10-22

申请人： Michio Horiuchi ,  Kazunari Imai

发明人： Michio Horiuchi ,  Kazunari Imai

IPC分类号： H01L2348

CPC分类号： H01L23/49827 ,  H01L23/3114 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/3473 ,  H05K3/4038 ,  H05K3/423 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2203/0733 ,  H01L2224/05599

摘要： A semiconductor device that meets the demand for realizing semiconductor chips in small sizes. A semiconductor device in which connection lands 20 formed on the electrode terminal carrying surface of a semiconductor chip 10 are electrically connected, through connection bumps 14, to connection pads 22 formed on one surface of an interposing substrate 12 of an insulating material so as to face the connection lands 20, wherein conductor wiring patterns 24 inclusive of the connection pads 22 are formed on one surface of the interposing substrate 12, conductor wiring patterns 30 inclusive of terminal lands on where the external connection terminals 26 will be mounted, are formed on the other surface of the interposing substrate 12, and the conductor wiring patterns 24 formed on one surface of the interposing substrate 12 are connected to the conductor wiring patterns 30 formed on the other surface of the interposing substrate 12 through vias 32 formed by filling recesses with a metal by plating, the recesses being formed to penetrate through the insulating material of the interposing substrate 12 and permitting the back surfaces of the conductor wiring patterns 24 on the side of the insulating material to be exposed on the bottom surfaces thereof.

摘要翻译： 一种满足小尺寸半导体芯片实现需求的半导体器件。 形成在半导体芯片10的电极端子承载表面上的连接焊盘20通过连接凸块14电连接到形成在绝缘材料的插入基板12的一个表面上的连接焊盘22的半导体器件， 连接焊盘20，其中包括连接焊盘22的导体布线图案24形成在插入基板12的一个表面上，导体布线图案30包括将安装外部连接端子26的端子焊盘的导体布线图案30形成在 插入基板12的另一个表面和形成在插入基板12的一个表面上的导体布线图案24通过通孔32连接到形成在插入基板12的另一个表面上的导体布线图案30， 通过电镀形成金属，所述凹部形成为穿透插入物的绝缘材料 g基板12，并且使绝缘材料侧的导体布线图案24的背面露出在其底面上。

公开(公告)号：US06271478B1

公开(公告)日：2001-08-07

申请号：US09195831

申请日：1998-11-19

申请人： Michio Horiuchi ,  Yukiharu Takeuchi ,  Chiaki Takubo

发明人： Michio Horiuchi ,  Yukiharu Takeuchi ,  Chiaki Takubo

IPC分类号： H05K114

CPC分类号： H05K1/112 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K2201/09227 ,  H05K2201/10734

摘要： A multi-layer circuit board having a decreased number of circuit boards for mounting an electronic part that has connection electrodes arranged in the form of an area array, featuring a high yield and improved reliability. In the multi-layer circuit board, circuit patterns formed on a first circuit board on the surface of the side where said electronic part is mounted, are connected to every land positioned on the outermost side of the lands arranged in the form of an area array, and are connected to the lands alternatingly selected from the lands of the second sequence and the third sequence of the inner side; circuit patterns formed on a second circuit board are connected to every via electrically connected to the lands of the second sequence to which the circuit pattern is not connected on the first circuit board, and to the vias electrically connected to all of the lands of the fourth sequence and the fifth sequence on the first circuit board; circuit patterns formed on a third circuit board are connected to every via electrically connected to the lands of the third sequence to which the circuit pattern is not connected on the first circuit board, and to the vias electrically connected to all of the lands of the sixth sequence and the seventh sequence on the first circuit board; and circuit patterns formed on a fourth circuit board are connected to every via electrically connected to the lands of the eighth sequence and the ninth sequence on the first circuit board.

摘要翻译： 一种多层电路板，其具有用于安装具有以区域阵列形式布置的连接电极的电子部件的电路板数量减少，具有高产量和改善的可靠性。 在多层电路板中，形成在安装有所述电子部件的一侧的表面上的第一电路板上的电路图案连接到位于以区域阵列形式布置的焊盘的最外侧的每个区域 并且连接到从第二序列的焊盘和内侧的第三序列交替地选择的焊盘; 形成在第二电路板上的电路图案连接到电连接到第一电路板上未连接电路图案的第二序列的焊盘的每个通孔，以及电连接到第四电路板的所有焊盘的通孔 序列和第一个电路板上的第五个序列; 形成在第三电路板上的电路图案连接到电连接到第一电路板上未连接电路图案的第三序列的焊盘的每个通孔，以及电连接到第六电路板的所有焊盘的通孔 序列和第七个序列在第一个电路板上; 并且形成在第四电路板上的电路图案连接到电连接到第一电路板上的第八序列和第九序列的焊盘的每个通孔。

公开(公告)号：US06093476A

公开(公告)日：2000-07-25

申请号：US71875

申请日：1998-05-01

申请人： Michio Horiuchi ,  Yukiharu Takeuchi

发明人： Michio Horiuchi ,  Yukiharu Takeuchi

IPC分类号： H05K1/02 ,  H01L21/48 ,  H01L23/12 ,  H01L23/13 ,  H01L23/15 ,  H01L23/498 ,  H05K1/00 ,  B32B3/06

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/13 ,  H01L23/15 ,  H05K1/0287 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32188 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01012 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/24926

摘要： A wiring substrate is provided in which a common core member is used and the cost can be reduced. Diameters of the penetrating filled vias (18) are the same and not more than 300 .mu.m, and the penetrating filled vias (18) are formed on a core substrate (20) into a matrix-shape at regular intervals of not more than 2 mm. On the surface of the core substrate (20), a plane wiring pattern (17) is formed through an insulating layer (16). Each pad portion on the wiring pattern (17) is electrically connected with each corresponding via of the filled vias (18) by one to one through a connecting via (28) which penetrates the insulating layer (16), and some of the filled vias (18) are not connected with the wiring pattern (17).

摘要翻译： 提供一种布线基板，其中使用共同的芯构件并且可以降低成本。 穿透填充过孔（18）的直径相同且不大于300μm，并且穿透填充的通孔（18）以不大于2的规则间隔在芯基板（20）上形成矩阵形状 mm。 在芯基板（20）的表面上，通过绝缘层（16）形成平面布线图案（17）。 布线图案（17）上的每个焊盘部分通过穿过绝缘层（16）的连接通孔（28）与填充的通孔（18）的每个相应的通孔电连接一个一个，并且一些填充的通孔 （18）不与布线图案17连接。

公开(公告)号：US5737191A

公开(公告)日：1998-04-07

申请号：US628346

申请日：1996-04-05

申请人： Michio Horiuchi ,  Yoichi Harayama

发明人： Michio Horiuchi ,  Yoichi Harayama

IPC分类号： H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H05K7/02

CPC分类号： H01L23/3675 ,  H01L21/563 ,  H01L23/29 ,  H01L23/3135 ,  H01L23/3164 ,  H01L23/49816 ,  H01L24/31 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/83951 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/15787

摘要： A semiconductor chip mount structure includes a substrate having a base surface on which base side connectors are formed; a semiconductor chip mounted on the base surface, the semiconductor chip having chip side connectors on a first surface thereof facing the base surface, the chip side connectors being electrically connected to the base side connectors; an insulating resin layer covering the chip side connectors and the base side connectors; a metal layer, made of a metal having a melting point lower than a temperature at which the electrical components of the semiconductor chip may be thermally destroyed, for covering the semiconductor chip and the insulating resin layer; and a wetting characteristic improving layer such as a metal powder or foil layer, formed along a contact surface between the metal layer and the insulation resin layer.

摘要翻译： 一种半导体芯片安装结构，包括具有形成有基极侧连接器的基面的基板; 半导体芯片安装在基底表面上，半导体芯片在其第一表面上具有面向基面的芯片侧连接器，芯片侧连接器电连接到基座侧连接器; 覆盖芯片侧连接器和基座侧连接器的绝缘树脂层; 金属层，其熔点低于半导体芯片的电气部件可能被热破坏的温度的金属制成，用于覆盖半导体芯片和绝缘树脂层; 以及沿金属层和绝缘树脂层之间的接触面形成的润湿特性改善层，例如金属粉末或箔层。

公开(公告)号：US5683791A

公开(公告)日：1997-11-04

申请号：US689692

申请日：1996-08-13

申请人： Michio Horiuchi ,  Yoichi Harayama

发明人： Michio Horiuchi ,  Yoichi Harayama

IPC分类号： H05K1/03 ,  B32B37/18 ,  H01L21/48 ,  H05K1/09 ,  H05K3/12 ,  H05K3/24 ,  H05K3/26 ,  H05K3/40 ,  H05K3/46 ,  B32B3/00 ,  B32B15/00

CPC分类号： B32B37/18 ,  H01L21/4857 ,  H01L21/486 ,  H05K1/092 ,  H05K3/4061 ,  H05K1/0306 ,  H05K2201/0317 ,  H05K2203/025 ,  H05K2203/1383 ,  H05K3/245 ,  H05K3/4611 ,  H05K3/4629 ,  Y10S428/901 ,  Y10T156/10 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/252

摘要： Internal wiring made of copper of low-resistance is provided in a ceramic oxide. Green sheets 10 made of oxide powder are provided with plane wiring 18 and/or via wiring 14 in which copper is used as wiring material. The green sheets 10 are laminated and integrated in such a manner that the wiring portions 4 and 18 are covered with the green sheet so as not to be exposed onto a surface. Then the laminated body is fired at a maximum temperature in a range from 1,083.degree. to 1,800.degree. C.

摘要翻译： 在陶瓷氧化物中设置由低电阻铜制成的内部布线。 由氧化物粉末制成的生片10具有平面布线18和/或通过其中使用铜作为布线材料的布线14。 生片10以这样的方式层叠并整合，使得布线部分4和18被生片覆盖，以便不暴露在表面上。 然后将层压体在最高温度为1083℃至1800℃的范围内烧制。