公开(公告)号：US09761677B2

公开(公告)日：2017-09-12

申请号：US15184570

申请日：2016-06-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Wen Liu ,  Chao-Hsiung Wang

IPC分类号： H01L29/423 ,  H01L29/41 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/285 ,  H01L21/74 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/40 ,  H01L23/482 ,  H01L29/66 ,  H01L27/118 ,  H01L29/78

CPC分类号： H01L29/41 ,  H01L21/28 ,  H01L21/28114 ,  H01L21/28587 ,  H01L21/3213 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/743 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76886 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/4827 ,  H01L29/40 ,  H01L29/66795 ,  H01L29/785 ,  H01L2027/11866 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/13067 ,  H01L2924/00

摘要： An embodiment includes a substrate, wherein a portion of the substrate extends upwards forming a fin, a gate dielectric over a top surface and at least portions of sidewalls of the fin, a gate electrode over the gate dielectric, and a contact over and extending into the gate electrode, wherein the contact has a first width above the gate electrode and a second width within the gate electrode, the first width being smaller than the second width.

公开(公告)号：US20170213736A1

公开(公告)日：2017-07-27

申请号：US15483273

申请日：2017-04-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： JOEL P. de SOUZA ,  BAHMAN HEKMATSHOARTABARI ,  JEEHWAN KIM ,  SIEGFRIED L. MAURER ,  DEVENDRA K. SADANA

IPC分类号： H01L21/283 ,  H01L29/66 ,  H01L29/40 ,  H01L21/3213 ,  H01L29/08

CPC分类号： H01L21/283 ,  A23C9/123 ,  A23C9/1315 ,  A23C11/08 ,  H01L21/2254 ,  H01L21/28114 ,  H01L21/30604 ,  H01L21/3213 ,  H01L21/32131 ,  H01L21/32133 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/66446 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78

摘要： A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.

公开(公告)号：US20170186911A1

公开(公告)日：2017-06-29

申请号：US15508899

申请日：2015-09-02

申请人： OSRAM Opto Semiconductors GmbH

发明人： Isabel OTTO ,  Alexander F. PFEUFFER ,  Dominik SCHOLZ

IPC分类号： H01L33/08 ,  H01L33/38

CPC分类号： H01L33/08 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/461 ,  H01L25/167 ,  H01L27/156 ,  H01L31/12 ,  H01L33/00 ,  H01L33/38 ,  H01L2933/0016 ,  H01L2933/0033

摘要： A method is specified for producing an optoelectronic semiconductor component, comprising the following steps: A) providing a structured semiconductor layer sequence (21, 22, 23) having —a first semiconductor layer (21) with a base region (21c), at least one well (211), and a first cover region (21a) in the region of the well (211) facing away from the base surface (21c), —an active layer (23), and —a second semiconductor layer (22) on a side of the active layer (23) facing away from the first semiconductor layer (21), wherein —the active layer (23) and the second semiconductor layer (22) are structured jointly in a plurality of regions (221, 231) and each region (221, 231) forms, together with the first semiconductor layer (21), an emission region (3), B) simultaneous application of a first contact layer (41) on the first cover surface (21a) and a second contact layer (42) on a second cover surface (3a) of the emission regions (3) facing away from the first semiconductor layer (21) in such a way that —the first contact layer (41) and the second contact layer (42) are electrically separated from each other, and —the first contact layer (41) and the second contact layer (42) run parallel to each other.

公开(公告)号：US20170117357A1

公开(公告)日：2017-04-27

申请号：US15402929

申请日：2017-01-10

申请人： International Business Machines Corporation

发明人： Praneet Adusumilli ,  Alexander Reznicek ,  Oscar Van der Straten ,  Chih-Chao Yang

IPC分类号： H01L29/06 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L29/0649 ,  H01L21/02164 ,  H01L21/265 ,  H01L21/31 ,  H01L21/31144 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

摘要： Aspects of the invention are directed to a method for forming a semiconductor device. A dielectric layer is formed on a semiconductor substrate. Subsequently, a metallic contact is formed in the dielectric layer such that it lands on the semiconductor substrate. A masking layer comprising a block copolymer is then formed on the dielectric layer. This block copolymer is caused to separate into two phases. One of the two phases is selectively removed to leave a patterned masking layer. The patterned masking layer is used to etch the dielectric layer. The patterned air gaps reduce the interconnect capacitance of the semiconductor device while leaving the dielectric layer with enough mechanical strength to serve as a middle-of-line dielectric.

公开(公告)号：US20170084723A1

公开(公告)日：2017-03-23

申请号：US14951593

申请日：2015-11-25

申请人： International Business Machines Corporation

发明人： Andrew M. Greene ,  Balasubramanian P. Haran ,  Injo Ok ,  Charan V. Surisetty

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3213

CPC分类号： H01L29/66545 ,  H01L21/28079 ,  H01L21/3213 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7856 ,  H01L2029/7858

摘要： A technique relates to forming a semiconductor device. A starting semiconductor device having a fin structure patterned in a substrate, and a gate formed over the fin structure, the gate having a mid-region and an end-region is first provided. A trench is then patterned over the mid-region of the gate and a trench is patterned over the end-region of the gate. The patterned trenches are then etched over the mid-region of the gate and the end-region of the gate to form the trenches. A conformal low-k dielectric layer can then be deposited over the structure to fill the trenches and pinch off the trench formed in the mid-region and the trench formed in the end-region.

公开(公告)号：US20170084463A1

公开(公告)日：2017-03-23

申请号：US14858628

申请日：2015-09-18

申请人： International Business Machines Corporation

发明人： Andrew M. Greene ,  Balasubramanian P. Haran ,  Injo Ok ,  Charan V. Surisetty

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L21/306 ,  H01L29/66 ,  H01L21/308 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L21/28079 ,  H01L21/3213 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7856 ,  H01L2029/7858

摘要： A technique relates to forming a semiconductor device. A starting semiconductor device having a fin structure patterned in a substrate, and a gate formed over the fin structure, the gate having a mid-region and an end-region is first provided. A trench is then patterned over the mid-region of the gate and a trench is patterned over the end-region of the gate. The patterned trenches are then etched over the mid-region of the gate and the end-region of the gate to form the trenches. A conformal low-k dielectric layer can then be deposited over the structure to fill the trenches and pinch off the trench formed in the mid-region and the trench formed in the end-region.

公开(公告)号：US20170004974A1

公开(公告)日：2017-01-05

申请号：US15185282

申请日：2016-06-17

申请人： Applied Materials, Inc.

发明人： Pramit MANNA ,  Abhijit Basu MALLICK

IPC分类号： H01L21/3105 ,  H01L21/311 ,  H01L21/02

CPC分类号： H01L21/02164 ,  C23C16/02 ,  C23C16/045 ,  C23C16/401 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02312 ,  H01L21/02315 ,  H01L21/033 ,  H01L21/0337 ,  H01L21/3213 ,  H01L21/76281 ,  H01L21/76283

摘要： Embodiments described herein generally provide a method for filling features formed on a substrate. In one embodiment, a method for selectively forming a silicon oxide layer on a substrate is provided. The method includes selectively depositing a silicon oxide layer within a patterned feature formed on a surface of a substrate, wherein the patterned feature comprises one or more sidewalls and a deposition surface at a bottom of the patterned feature, the one or more sidewalls comprise a silicon oxide, a silicon nitride, or a combination thereof, the deposition surface essentially consists of silicon, and the selectively deposited silicon oxide layer is formed on the deposition surface by flowing tetraethyl orthosilicate (TEOS) and ozone over the patterned feature.

摘要翻译： 本文描述的实施例通常提供用于填充形成在基底上的特征的方法。 在一个实施例中，提供了在衬底上选择性地形成氧化硅层的方法。 该方法包括在形成在衬底的表面上的图案化特征中选择性地沉积氧化硅层，其中图案化特征包括在图案化特征的底部的一个或多个侧壁和沉积表面，所述一个或多个侧壁包括硅 氧化物，氮化硅或其组合，沉积表面基本上由硅组成，并且通过在图案化特征上流动原硅酸四乙酯（TEOS）和臭氧，在沉积表面上形成选择性沉积的氧化硅层。

公开(公告)号：US20160300720A1

公开(公告)日：2016-10-13

申请号：US15184570

申请日：2016-06-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Wen Liu ,  Chao-Hsiung Wang

IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/74

CPC分类号： H01L29/41 ,  H01L21/28 ,  H01L21/28114 ,  H01L21/28587 ,  H01L21/3213 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/743 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76886 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/4827 ,  H01L29/40 ,  H01L29/66795 ,  H01L29/785 ,  H01L2027/11866 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/13067 ,  H01L2924/00

摘要： An embodiment includes a substrate, wherein a portion of the substrate extends upwards forming a fin, a gate dielectric over a top surface and at least portions of sidewalls of the fin, a gate electrode over the gate dielectric, and a contact over and extending into the gate electrode, wherein the contact has a first width above the gate electrode and a second width within the gate electrode, the first width being smaller than the second width.

摘要翻译： 一个实施例包括一个衬底，其中衬底的一部分向上延伸形成翅片，位于顶表面上的栅极电介质和鳍的侧壁的至少部分，栅极电介质上的栅电极， 所述栅电极，其中所述触点具有所述栅电极上方的第一宽度和所述栅电极内的第二宽度，所述第一宽度小于所述第二宽度。

公开(公告)号：US20160208141A1

公开(公告)日：2016-07-21

申请号：US14597737

申请日：2015-01-15

申请人： UWiZ Technology Co., Ltd.

发明人： Yun Lung Ho ,  Chun Chieh Lee ,  Song Yuan Chang ,  Ming Hui Lu ,  Ming Che Ho

IPC分类号： C09G1/02

CPC分类号： C09G1/02 ,  C09G1/00 ,  H01L21/3212 ,  H01L21/3213

摘要： A polishing composition comprising abrasive particles, a compound having hexavalent molybdenum or pentavalent vanadium, an anionic additive, a halogen oxides compound or salts thereof, and a carrier solvent is provided herein. The polishing composition is suitable for chemical mechanical polishing process of SiGe, Si and SiO2 substrates. The compound having hexavalent molybdenum or pentavalent can effectively raise the removal rate for SiGe and Si substrates, and increase the polishing selectivity of SiGe and Si relative to SiO2, simultaneously.

摘要翻译： 本文提供了包含磨粒，具有六价钼或五价钒的化合物，阴离子添加剂，卤素氧化物或其盐以及载体溶剂的抛光组合物。 抛光组合物适用于SiGe，Si和SiO2基板的化学机械抛光工艺。 具有六价钼或五价的化合物可以有效地提高SiGe和Si衬底的去除率，同时提高SiGe和Si相对于SiO2的抛光选择性。

公开(公告)号：US09373652B2

公开(公告)日：2016-06-21

申请号：US14806221

申请日：2015-07-22

申请人： Samsung Display Co., Ltd.

发明人： Guanghai Jin ,  Nayoung Kim

IPC分类号： H01L29/12 ,  H01L27/12 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L27/1259 ,  H01L21/3213 ,  H01L27/1255 ,  H01L27/3258 ,  H01L27/3265 ,  H01L29/66757 ,  H01L29/78666 ,  H01L29/78675

摘要： Provided are a display apparatus and a method of manufacturing the display apparatus. The display apparatus includes: a substrate having a major surface; and a capacitor disposed over the substrate. The capacitor includes a first electrode, and a second electrode disposed over the first electrode. The second electrode includes a first region, a second region and an opening when viewed in a direction perpendicular to the major surface. The first region has a first thickness, and a second region has a second thickness that is greater than the first thickness.

摘要翻译： 提供一种显示装置和制造该显示装置的方法。 显示装置包括：具有主表面的基板; 以及设置在基板上的电容器。 电容器包括第一电极和设置在第一电极上的第二电极。 当从垂直于主表面的方向观察时，第二电极包括第一区域，第二区域和开口。 第一区域具有第一厚度，第二区域具有大于第一厚度的第二厚度。