公开(公告)号：US07234218B2

公开(公告)日：2007-06-26

申请号：US10906816

申请日：2005-03-08

申请人： Mukta G. Farooq ,  Harvey C. Hamel

发明人： Mukta G. Farooq ,  Harvey C. Hamel

IPC分类号： B23P19/02

CPC分类号： H05K3/3494 ,  B23K1/018 ,  B23K2101/40 ,  H01L24/98 ,  H01L2224/81222 ,  H01L2224/81234 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K1/0212 ,  H05K3/3436 ,  H05K2203/176 ,  Y10T29/49144 ,  Y10T29/49721 ,  Y10T29/49815 ,  Y10T29/49819 ,  Y10T29/49821 ,  H01L2924/00

摘要： A method and electrical structure for separating electronic components from one another joined by solder interconnections. An electronic module is joined to a substrate via a solder interconnection, whereby the electronic module has an electrical heating component residing within a bottom layer thereof adjacent a solder interconnection. Preferably, a chip carrier is joined to a board whereby the chip carrier has an electrical mesh plane for heating adjacent the solder interconnection. Resistive heat is generated within this electrical heating component either by applying an electrical current to the electrical heating component, or by non-contact inductively heating the layer in which such electrical heating component resides to generate resistive heat within the electrical heating component. The resistive heat is transferred to the solder interconnection to allow for localized melting of the solder interconnection and removal of the electronic components from one another.

摘要翻译： 一种用于将电子部件彼此分离以通过焊料互连连接的方法和电气结构。 电子模块通过焊料互连连接到基板，由此电子模块具有驻留在其邻近焊料互连的底层内的电加热部件。 优选地，芯片载体连接到板，由此芯片载体具有用于在焊料互连附近加热的电网平面。 通过向电加热部件施加电流，或通过非接触感应加热这种电加热部件所在的层以在电加热部件内产生电阻热，在该电加热部件内产生电阻热。 电阻热转移到焊料互连以允许焊料互连的局部熔化和电子部件相互之间的移除。

公开(公告)号：US07170187B2

公开(公告)日：2007-01-30

申请号：US10711185

申请日：2004-08-31

申请人： William E. Bernier ,  Marie S. Cole ,  Mukta G. Farooq ,  John U. Knickerbocker ,  Tasha E. Lopez ,  Roger A. Quon ,  David J. Welsh

发明人： William E. Bernier ,  Marie S. Cole ,  Mukta G. Farooq ,  John U. Knickerbocker ,  Tasha E. Lopez ,  Roger A. Quon ,  David J. Welsh

IPC分类号： H01L23/48

CPC分类号： H05K3/321 ,  H01L24/05 ,  H01L24/12 ,  H01L24/16 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13339 ,  H01L2224/13464 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H05K2201/0212 ,  H05K2201/0248 ,  H05K2201/0373 ,  H05K2201/1025 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/00015 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

摘要： Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.

摘要翻译： 公开了用于将集成电路器件连接到器件载体的层压（或非层叠）导电互连，其中导电互连包括交替的金属层和聚合物层。 此外，聚合物可以包括枝晶，来自载体或器件的金属突起，和/或聚合物外部的胶束刷。 聚合物层包括金属颗粒，并且交替的金属层和聚合物层形成立方体结构或圆柱形结构。

公开(公告)号：US06987316B2

公开(公告)日：2006-01-17

申请号：US10707810

申请日：2004-01-14

申请人： Srinivasa N. Reddy ,  Mukta G. Farooq ,  Kevin M. Prettyman

发明人： Srinivasa N. Reddy ,  Mukta G. Farooq ,  Kevin M. Prettyman

IPC分类号： H01L23/06 ,  H01L23/10 ,  H01L23/15

CPC分类号： H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/113 ,  H05K2201/096 ,  H01L2924/00

摘要： A multilayer ceramic substrate in which an outer metal pad is anchored to the substrate by a single metal-filled via in the first ceramic layer adjacent to the metal pad. In turn, this single metal-filled via is anchored to the substrate by a larger, single metal-filled via in the next ceramic layer adjacent to the first ceramic layer. Preferably, the metal-filled vias and metal pad are 100 volume percent metal.

摘要翻译： 一种多层陶瓷基板，其中外金属焊盘通过与金属焊盘相邻的第一陶瓷层中的单个金属填充通孔锚定到基板。 反过来，通过在与第一陶瓷层相邻的下一个陶瓷层中的较大的单个金属填充的通孔将该单个金属填充的通孔锚定到衬底。 优选地，金属填充的通孔和金属垫是100体积％的金属。

公开(公告)号：US09406561B2

公开(公告)日：2016-08-02

申请号：US12426466

申请日：2009-04-20

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Emily R. Kinser

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Emily R. Kinser

IPC分类号： H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L21/76898 ,  H01L24/06 ,  H01L24/80 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/80896 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2924/00

摘要： A method of implementing three-dimensional (3D) integration of multiple integrated circuit (IC) devices includes forming a first insulating layer over a first IC device; forming a second insulating layer over a second IC device; forming a 3D, bonded IC device by aligning and bonding the first insulating layer to the second insulating layer so as to define a bonding interface therebetween, defining a first set of vias within the 3D bonded IC device, the first set of vias landing on conductive pads located within the first IC device, and defining a second set of vias within the 3D bonded IC device, the second set of vias landing on conductive pads located within the second device, such that the second set of vias passes through the bonding interface; and filling the first and second sets of vias with a conductive material.

摘要翻译： 实现多集成电路（IC）器件的三维（3D）集成的方法包括在第一IC器件上形成第一绝缘层; 在第二IC器件上形成第二绝缘层; 通过将第一绝缘层对准和结合到第二绝缘层来形成3D粘合IC器件，以便在它们之间限定其间的接合界面，限定3D结合IC器件内的第一组通孔，第一组通孔在导电 位于所述第一IC器件内的焊盘，以及限定所述3D结合IC器件内的第二组通孔，所述第二组通孔着陆在位于所述第二器件内的导电焊盘上，使得所述第二组通孔穿过所述接合界面; 以及用导电材料填充第一组和第二组通孔。

公开(公告)号：US09059175B2

公开(公告)日：2015-06-16

申请号：US13297338

申请日：2011-11-16

申请人： Mukta G. Farooq ,  Emily R. Kinser

发明人： Mukta G. Farooq ,  Emily R. Kinser

IPC分类号： H01L23/62 ,  H01L23/525 ,  H01L27/10

CPC分类号： H01L23/5258 ,  H01L23/5256 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, the invention provides a back-end-of-line (BEOL) line fuse structure. The BEOL line fuse structure includes: a line including a plurality of grains of conductive crystalline material; wherein the plurality of grains in a region between the first end and a second end include an average grain size that is smaller than a nominal grain size of the plurality of grains in a remaining portion of the line.

摘要翻译： 在一个实施例中，本发明提供一种后端行（BEOL）线路熔丝结构。 BEOL线熔丝结构包括：包括多个导电结晶材料颗粒的线; 其中在所述第一端和第二端之间的区域中的所述多个晶粒包括平均晶粒尺寸，所述平均晶粒尺寸小于所述线的剩余部分中所述多个晶粒的标称晶粒尺寸。

公开(公告)号：US20150024548A1

公开(公告)日：2015-01-22

申请号：US13572004

申请日：2012-08-10

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

IPC分类号： H01L25/065 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83121 ,  H01L2224/83895 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

摘要： A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.

摘要翻译： 提供了一种计算机可读介质，其由包含用于执行制造3D集成电路结构的方法的指令的程序编码。 提供了包括第一布线层和穿硅通孔的接口晶片，以及包括有源电路的第一有源电路层晶片。 第一有源电路层晶片被结合到界面晶片。 然后，去除第一有源电路层晶片的第一部分，使得第二部分保持附着到界面晶片。 包括接口晶片和第一有源电路层晶片的第二部分的堆叠结构被结合到基底晶片。 接下来，将界面晶片减薄以形成界面层，并且在界面层上形成通过界面层中的穿硅通孔耦合到第一布线层的金属化。

公开(公告)号：US08841777B2

公开(公告)日：2014-09-23

申请号：US12685954

申请日：2010-01-12

申请人： Mukta G. Farooq ,  Zhengwen Li ,  Zhijiong Luo ,  Huilong Zhu

发明人： Mukta G. Farooq ,  Zhengwen Li ,  Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L21/48 ,  H01L21/52 ,  H01L21/40 ,  H01L21/20 ,  H01L27/06 ,  H01L21/768

CPC分类号： H01L21/76841 ,  H01L21/2007 ,  H01L27/0688 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896

摘要： Vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with vertical stacks of a metal portion and a semiconductor portion formed on a second substrate. Alternately, vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with metal portions formed on a second substrate. The assembly of the first and second substrates is subjected to an anneal at a temperature that induces formation of a metal semiconductor alloy derived from the semiconductor portions and the metal portions. The first substrate and the second substrate are bonded through metal semiconductor alloy portions that adhere to the first and second substrates.

摘要翻译： 形成在第一基板上的金属部分和半导体部分的垂直叠层与形成在第二基板上的金属部分和半导体部分的垂直叠层物理接触。 或者，形成在第一基板上的金属部分和半导体部分的垂直堆叠与形成在第二基板上的金属部分物理接触。 在引起由半导体部分和金属部分衍生的金属半导体合金的形成的温度下对第一和第二基板的组装进行退火。 第一基板和第二基板通过粘附到第一和第二基板的金属半导体合金部分接合。

公开(公告)号：US08791005B2

公开(公告)日：2014-07-29

申请号：US13525823

申请日：2012-06-18

申请人： Mukta G. Farooq ,  John A. Fitzsimmons ,  Troy L. Graves-Abe

发明人： Mukta G. Farooq ,  John A. Fitzsimmons ,  Troy L. Graves-Abe

IPC分类号： H01L23/532

CPC分类号： H05K3/423 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53257 ,  H01L2924/0002 ,  Y10T428/12764 ,  H01L2924/00

摘要： A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material. The structure including a first intermetallic compound separating the diffusion barrier from the conductive material, the first intermetallic compound comprises an alloying material and the conductive material, and is mechanically bound to the conductive material, the alloying material is at least one of the materials selected from the group of chromium, tin, nickel, magnesium, cobalt, aluminum, manganese, titanium, zirconium, indium, palladium, and silver; and a first high friction interface located between the diffusion barrier and the first intermetallic compound and parallel to the sidewall of the opening, wherein the first high friction interface results in a mechanical bond between the diffusion barrier and the first intermetallic compound.

摘要翻译： 一种形成在开口中的结构，其具有由非金属材料限定的基本上垂直的侧壁，并且具有由导电垫限定的基本上水平的底部，该结构包括覆盖侧壁的扩散阻挡层和由导电材料构成的填充物。 所述结构包括将所述扩散阻挡物与所述导电材料分离的第一金属间化合物，所述第一金属间化合物包括合金材料和所述导电材料，并且机械地结合到所述导电材料上，所述合金材料是选自以下的至少一种材料： 铬，锡，镍，镁，钴，铝，锰，钛，锆，铟，钯和银的组合; 以及位于所述扩散阻挡层和所述第一金属间化合物之间且平行于所述开口的侧壁的第一高摩擦界面，其中所述第一高摩擦界面导致所述扩散阻挡层和所述第一金属间化合物之间的机械结合。

公开(公告)号：US08738167B2

公开(公告)日：2014-05-27

申请号：US13398481

申请日：2012-02-16

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Sampath Purushothaman ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Sampath Purushothaman ,  Roy R. Yu

IPC分类号： G06F19/00 ,  H01L21/30 ,  H01L21/46 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L27/105 ,  H01L24/11 ,  H01L27/0688 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599

摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a non-transitory computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

摘要翻译： 提供了一种用于制造3D集成电路结构的方法。 根据该方法，提供第一有源电路层晶片。 第一有源电路层晶片包括由P层覆盖的P +部分，并且P层包括有源电路。 第一有源电路层晶片面向下接合到包括第一布线层的接口晶片，然后相对于第一有源电路层晶片的P层选择性地去除第一有源电路层晶片的P +部分 。 接下来，在P-层的背面上制造布线层。 还提供了编码有用于制造3D集成电路结构的程序的非暂时计算机可读介质，以及3D集成电路结构。

公开(公告)号：US08709936B2

公开(公告)日：2014-04-29

申请号：US13562927

申请日：2012-07-31

申请人： Richard P. Volant ,  Mukta G. Farooq

发明人： Richard P. Volant ,  Mukta G. Farooq

IPC分类号： H01L21/00

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/53295 ,  H01L24/05 ,  H01L2224/05647 ,  H01L2924/00014

摘要： A method, and the resulting structure, to make a thinned substrate with backside redistribution wiring connected to through silicon vias of varying height. The method includes thinning a backside of a substrate to expose through silicon vias. Then a thick insulator stack, including an etch stop layer, is deposited and planarized. With a planar insulating surface in place, openings in the insulator stack can be formed by etching. The etch stop layer in the dielectric stack accommodates the differing heights vias. The etch stop is removed and a conductor having a liner is formed in the opening. The method gives a unique structure in which a liner around the bottom of the through silicon via remains in tact. Thus, the liner of the via and a liner of the conductor meet to form a double liner at the via/conductor junction.

摘要翻译： 一种方法和所得到的结构，使得具有通过不同高度的硅通孔连接到背侧再分布布线的薄化基板。 该方法包括使衬底的背面变薄以通过硅通孔暴露。 然后沉积包括蚀刻停止层的厚的绝缘体堆叠并平坦化。 通过平面绝缘表面就可以通过蚀刻形成绝缘体堆叠中的开口。 电介质堆叠中的蚀刻停止层容纳不同的高度通孔。 去除蚀刻停止件，并且在开口中形成具有衬垫的导体。 该方法提供了一种独特的结构，其中通过硅通孔底部的衬垫仍然保持平衡。 因此，通孔的衬垫和导体的衬垫在通孔/导体结处相交以形成双衬垫。