公开(公告)号：US09337282B2

公开(公告)日：2016-05-10

申请号：US13962218

申请日：2013-08-08

申请人： FUJI ELECTRIC CO., LTD.

发明人： Shoji Kitamura

IPC分类号： H01L29/36 ,  H01L21/22 ,  H01L21/263 ,  H01L29/66 ,  H01L29/861 ,  H01L21/3105 ,  H01L21/311

CPC分类号： H01L29/868 ,  H01L21/22 ,  H01L21/221 ,  H01L21/225 ,  H01L21/263 ,  H01L21/3105 ,  H01L21/31111 ,  H01L29/063 ,  H01L29/36 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/66204 ,  H01L29/861

摘要： A simplified manufacturing process stably produces a semiconductor device with high electrical characteristics, wherein platinum acts as an acceptor. Plasma treatment damages the surface of an oxide film formed on a n− type drift layer deposited on an n+ type semiconductor substrate. The oxide film is patterned to have tapered ends. Two proton irradiations are carried out on the n− type drift layer with the oxide film as a mask to form a point defect region in the vicinity of the surface of the n− type drift layer. Silica paste containing 1% by weight platinum is applied to an exposed region of the n− type drift layer surface not covered with the oxide film. Heat treatment inverts the vicinity of the surface of the n− type drift layer to p-type by platinum atoms which are acceptors. A p-type inversion enhancement region forms a p-type anode region.

摘要翻译： 简化的制造工艺稳定地生产具有高电特性的半导体器件，其中铂作为受体。 等离子体处理破坏了沉积在n +型半导体衬底上的n型漂移层上形成的氧化物膜的表面。 图案化氧化膜以具有锥形末端。 在以氧化膜为掩模的n型漂移层上进行两个质子照射，以在n型漂移层的表面附近形成点缺陷区域。 将含有1重量％铂的二氧化硅浆料施加到未被氧化物膜覆盖的n型漂移层表面的露出区域。 热处理使n型漂移层的表面附近由接受体的铂原子反转成p型。 p型反转增强区域形成p型阳极区域。

公开(公告)号：US09330938B2

公开(公告)日：2016-05-03

申请号：US14340068

申请日：2014-07-24

申请人： International Business Machines Corporation

发明人： Takashi Ando ,  Hemanth Jagannathan ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Rekha Rajaram

IPC分类号： H01L21/76 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/321

CPC分类号： H01L21/823462 ,  H01L21/02321 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/225 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tinv (inverse of gate capacitance) mismatch.

摘要翻译： 使用替代金属栅极工艺制造先进节点场效应晶体管的方法。 该方法通过使用由多层薄膜堆叠构成的层，或者在其它实施方案中通过单个阻挡层直接或间接地包括掺杂剂高k电介质。 通过利用多层堆叠的意想不到的蚀刻选择性或单层堆叠的受控蚀刻工艺，可以避免对高k的蚀刻损伤，并且可以严格控制功函数金属厚度，这又可以实现场效应晶体管 具有低Tinv（栅极电容的倒数）不匹配。

公开(公告)号：US20160104768A1

公开(公告)日：2016-04-14

申请号：US14878565

申请日：2015-10-08

申请人： Infineon Technologies Austria AG

发明人： Armin Willmeroth ,  Franz Hirler ,  Hans Weber ,  Markus Schmitt ,  Thomas Wahls ,  Rolf Weis

IPC分类号： H01L29/06 ,  H01L21/324 ,  H01L21/225 ,  H01L21/266

CPC分类号： H01L29/0634 ,  H01L21/225 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/324 ,  H01L29/0696 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811

摘要： A super junction semiconductor device is formed by forming at least a portion of a drift layer on a doped layer of a first conductivity type, implanting first dopants of a first conductivity type and second dopants of a second conductivity type into the drift layer using one or more implant masks with openings to form stripe-shaped first implant regions of the first conductivity type and stripe-shaped second implant regions of the second conductivity type in alternating order, and performing a heat treatment for controlling a diffusion of dopants from the implant regions to form stripe-shaped first regions of the first conductivity type and stripe-shaped second regions of the second conductivity type.

摘要翻译： 通过在第一导电类型的掺杂层上形成漂移层的至少一部分，将第一导电类型的第一掺杂剂和第二导电类型的第二掺杂剂注入到漂移层中，使用一个或多个第一导电类型的掺杂层形成超结半导体器件， 更多具有开口的植入物掩模以交替的顺序形成第一导电类型的条形第一注入区域和第二导电类型的条形第二注入区域，并且执行热处理以控制掺杂剂从植入区域扩散到 形成第一导电类型的条形第一区域和第二导电类型的条形第二区域。

公开(公告)号：US20160079352A1

公开(公告)日：2016-03-17

申请号：US14951124

申请日：2015-11-24

申请人： Renesas Electronics Corporation

发明人： Tsuyoshi Kachi

IPC分类号： H01L29/06 ,  H01L21/324 ,  H01L21/225 ,  H01L29/66 ,  H01L21/265

CPC分类号： H01L29/0634 ,  H01L21/225 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

摘要： To realize a semiconductor device having a power MOSFET satisfying both a low conduction resistance and a high junction breakdown voltage by a simple and easy manufacturing method. Over an n-type substrate, a p-type epitaxial layer of a low concentration is formed, and, in an active part, a plurality of active regions is defined by a plurality of trenches that is formed in the epitaxial layer and extends in a first direction with first intervals in a second direction orthogonal to the first direction. In the epitaxial layer between the adjacent trenches, an n-type diffusion region that functions as a drain offset layer is formed, and, in the epitaxial layer between a side wall of the trench and the n-type diffusion region, a p-type diffusion region connected with a channel region (the p-type diffusion region) is formed, to constitute a super junction structure. Further, by forming an n-type diffusion region in the epitaxial layer, having a prescribed width from a side wall of a trench lying in the end part of the active part toward an outer periphery part, to achieve the improvement of a drain breakdown voltage.

摘要翻译： 通过简单且容易的制造方法实现具有满足低导通电阻和高结击穿电压的功率MOSFET的半导体器件。 在n型衬底上形成低浓度的p型外延层，并且在有源部分中，多个有源区由形成在外延层中的多个沟槽限定，并且在 第一方向在与第一方向正交的第二方向上具有第一间隔。 在相邻沟槽之间的外延层中，形成用作漏极偏移层的n型扩散区，并且在沟槽的侧壁和n型扩散区之间的外延层中，形成p型 形成与沟道区域（p型扩散区域）连接的扩散区域，构成超结构结构。 此外，通过在外延层中形成具有规定宽度的n型扩散区，从位于有源部的端部的沟槽的侧壁朝向外周部，具有规定的宽度，以实现漏极击穿电压的提高 。

公开(公告)号：US20160049477A1

公开(公告)日：2016-02-18

申请号：US14926077

申请日：2015-10-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Richard Kenneth OXLAND ,  Mark van DAL

IPC分类号： H01L29/207 ,  H01L29/08 ,  H01L21/225 ,  H01L21/31 ,  H01L21/02 ,  H01L21/324 ,  H01L21/306 ,  H01L29/66 ,  H01L29/205

CPC分类号： H01L29/207 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/225 ,  H01L21/2258 ,  H01L21/30612 ,  H01L21/31 ,  H01L21/3245 ,  H01L29/0847 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/6656 ,  H01L29/7834

摘要： A semiconductor device comprises a semiconductor substrate; a channel layer of at least one III-V semiconductor compound above the semiconductor substrate; a gate electrode above a first portion of the channel layer; a source region and a drain region above a second portion of the channel layer; and a dopant layer comprising at least one dopant contacting the second portion of the channel layer.

公开(公告)号：US20160027664A1

公开(公告)日：2016-01-28

申请号：US14340068

申请日：2014-07-24

申请人： International Business Machines Corporation

发明人： Takashi Ando ,  Hemanth Jagannathan ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Rekha Rajaram

IPC分类号： H01L21/3213 ,  H01L21/321 ,  H01L21/28

CPC分类号： H01L21/823462 ,  H01L21/02321 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/225 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tiny (inverse of gate capacitance) mismatch.

公开(公告)号：US09245989B2

公开(公告)日：2016-01-26

申请号：US13976414

申请日：2011-12-19

申请人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

发明人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC分类号： H01L29/775 ,  H01L29/66 ,  G05F3/02 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/20

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/225 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

摘要： Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, and drain and source contacts similarly coaxially wrap completely around the drain and source regions.

摘要翻译： 晶体管适用于高电压和高频工作。 纳米线垂直或水平地布置在基底上。 纳米线的纵向长度被限定为第一半导体材料的沟道区域，与沟道区域的第一端电耦合的源极区域，与沟道区域的第二端电耦合的漏极区域和外部漏极 区域设置在沟道区域和漏极区域之间。 外在漏极区具有比第一半导体更宽的带隙。 包括栅极导体和栅极绝缘体的栅极堆叠器完全同轴地包裹在沟道区域周围，并且漏极和源极触点类似地同轴地围绕漏极和源极区域包裹。

公开(公告)号：US20150357438A1

公开(公告)日：2015-12-10

申请号：US14680420

申请日：2015-04-07

申请人： UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.

发明人： FUJIO MASUOKA ,  NOZOMU HARADA

IPC分类号： H01L29/66 ,  H01L21/285 ,  H01L29/08 ,  H01L21/225 ,  H01L29/423 ,  H01L21/324

CPC分类号： H01L29/66666 ,  H01L21/225 ,  H01L21/28512 ,  H01L21/324 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/7827

摘要： An N+ region 2a and a P+ region 3a are formed in a Si pillar 6. HfO2 layers 9a and 9c, TiN layers 10b and 10d, and SiO2 layers 11b and 11d are formed to surround the Si pillar 6. Then contact portions 21a and 21b are respectively formed in side surfaces of the N+ region 2a and the P+ region 3a and a side surface of the TiN layer 10d. Then Si and Ni atoms are injected in a direction perpendicular to an upper surface of an i-layer substrate 1 from above the Si pillar 6 to form a Si layer and a Ni layer. Subsequently, a heat treatment is performed to expand NiSi layers 18a and 22 in a horizontal direction by Ni-silicidation. As a result, the NiSi layers 18a and 22 connect to the N+ region 2a and the P+ region 3a or the TiN layer 10d.

摘要翻译： 在Si支柱6上形成有N +区域2a和P +区域3a。形成HfO 2层9a，9c，TiN层10b，10d以及SiO 2层11b，11d，以包围Si柱6.然后，接触部21a，21b 分别形成在N +区域2a和P +区域3a的侧表面和TiN层10d的侧表面上。 然后从Si柱6上方向与i层基板1的上表面正交的方向注入Si和Ni原子，形成Si层和Ni层。 随后，通过Ni-硅化处理进行水平方向的NiSi层18a和22的热处理。 结果，NiSi层18a和22连接到N +区域2a和P +区域3a或TiN层10d。

公开(公告)号：US09209249B2

公开(公告)日：2015-12-08

申请号：US14149908

申请日：2014-01-08

申请人： Renesas Electronics Corporation

发明人： Tsuyoshi Kachi

IPC分类号： H01L29/76 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0634 ,  H01L21/225 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

摘要： To realize a semiconductor device having a power MOSFET satisfying both a low conduction resistance and a high junction breakdown voltage by a simple and easy manufacturing method. Over an n-type substrate, a p-type epitaxial layer of a low concentration is formed, and, in an active part, a plurality of active regions is defined by a plurality of trenches that is formed in the epitaxial layer and extends in a first direction with first intervals in a second direction orthogonal to the first direction. In the epitaxial layer between the adjacent trenches, an n-type diffusion region that functions as a drain offset layer is formed, and, in the epitaxial layer between a side wall of the trench and the n-type diffusion region, a p-type diffusion region connected with a channel region (the p-type diffusion region) is formed, to constitute a super junction structure. Further, by forming an n-type diffusion region in the epitaxial layer, having a prescribed width from a side wall of a trench lying in the end part of the active part toward an outer periphery part, to achieve the improvement of a drain breakdown voltage.

摘要翻译： 通过简单且容易的制造方法实现具有满足低导通电阻和高结击穿电压的功率MOSFET的半导体器件。 在n型衬底上形成低浓度的p型外延层，并且在有源部分中，多个有源区由形成在外延层中的多个沟槽限定，并且在 第一方向在与第一方向正交的第二方向上具有第一间隔。 在相邻沟槽之间的外延层中，形成用作漏极偏移层的n型扩散区，并且在沟槽的侧壁和n型扩散区之间的外延层中，形成p型 形成与沟道区域（p型扩散区域）连接的扩散区域，构成超结构结构。 此外，通过在外延层中形成具有规定宽度的n型扩散区，从位于有源部的端部的沟槽的侧壁朝向外周部，具有规定的宽度，以实现漏极击穿电压的提高 。

公开(公告)号：US20150349092A1

公开(公告)日：2015-12-03

申请号：US14821085

申请日：2015-08-07

申请人： Texas Instruments Incorporated

发明人： Marie DENISON ,  Sameer PENDHARKAR ,  Guru MATHUR

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/417 ,  H01L21/324 ,  H01L21/225 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265

CPC分类号： H01L29/66712 ,  H01L21/225 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66674 ,  H01L29/66734 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7813

摘要： A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region.