中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

184 records (took 0.048 seconds)

    PRINTED WIRING BOARD, SEMICONDUCTOR PACKAGE, AND PRINTED CIRCUIT BOARD
    81.
    发明申请
    PRINTED WIRING BOARD, SEMICONDUCTOR PACKAGE, AND PRINTED CIRCUIT BOARD 有权
    印刷电路板，半导体封装和印刷电路板

    公开(公告)号：US20130279134A1

    公开(公告)日：2013-10-24

    申请号：US13862038

    申请日：2013-04-12

    Applicant: CANON KABUSHIKI KAISHA

    Inventor： Seiji Hayashi ,  Takuya Kondo ,  Shoji Matsumoto

    IPC: H05K1/02

    CPC classification number: H05K1/0216 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/48227 ,  H05K1/0228 ,  H05K1/0242 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/114 ,  H05K1/116 ,  H05K1/14 ,  H05K1/141 ,  H05K1/162 ,  H05K1/18 ,  H05K2201/0939 ,  H05K2201/09418 ,  H05K2201/09454 ,  H05K2201/09463 ,  H05K2201/09636 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734

    Abstract: First and second signal wiring patterns are formed in a first conductor layer. A first electrode pad electrically connected to the first signal wiring pattern through a first via and a second electrode pad electrically connected to the second signal wiring pattern through a second via are formed in a second conductor layer as a surface layer. A third conductor layer is disposed between the first conductor layer and the second conductor layer with an insulator interposed between those conductor layers. A first pad electrically connected to the first via is formed in the third conductor layer. The first pad includes an opposed portion which overlaps the second electrode pad as viewed in a direction perpendicular to the surface of a printed board and which is opposed to the second electrode pad through intermediation of the insulator. This enables reduction of crosstalk noise caused between the signal wirings.

    Abstract translation: 第一和第二信号布线图案形成在第一导体层中。 通过第一通孔电连接到第一信号布线图案的第一电极焊盘和通过第二通孔电连接到第二信号布线图案的第二电极焊盘形成在作为表面层的第二导体层中。 第三导体层设置在第一导体层和第二导体层之间，绝缘体插在这些导体层之间。 电连接到第一通孔的第一焊盘形成在第三导体层中。 第一焊盘包括与垂直于印刷电路板的表面的方向观察的与第二电极焊盘重叠并且通过绝缘体与第二电极焊盘相对的相对部分。 这使得能够减少在信号布线之间引起的串扰噪声。

    CIRCUIT BOARD WITH AIR HOLE
    82.
    发明申请
    CIRCUIT BOARD WITH AIR HOLE 审中-公开
    具有空气孔的电路板

    公开(公告)号：US20130077268A1

    公开(公告)日：2013-03-28

    申请号：US13510477

    申请日：2010-11-18

    Applicant: David L. Brunker ,  David E. Dunham ,  Kent E. Regnier ,  Michael J. Neumann

    Inventor： David L. Brunker ,  David E. Dunham ,  Kent E. Regnier ,  Michael J. Neumann

    IPC: H05K1/11

    CPC classification number: H05K1/115 ,  H05K1/0219 ,  H05K1/024 ,  H05K1/0245 ,  H05K1/0251 ,  H05K2201/09063 ,  H05K2201/09618 ,  H05K2201/09636

    Abstract: A circuit board includes a first and second ground layer and a plurality of signal vias extending between the ground layers but not electrical contact therewith. Ground vias coupled to the first and second ground layers can be positioned adjacent signal vias and can include ground traces that extend between adjacent ground vias. Air holes can be positioned between signal vias and/or adjacent signal vias to modify the electrical performance of the circuit board. Ground wings can be used to help tune common-mode and/or differential-mode impedances.

    Abstract translation: 电路板包括第一和第二接地层以及在接地层之间延伸但不与其接触的多个信号通孔。 耦合到第一和第二接地层的接地通孔可以位于信号通孔附近，并且可以包括在相邻的接地通孔之间延伸的接地迹线。 气孔可以位于信号通道和/或相邻信号通道之间，以改变电路板的电气性能。 地面翼可用于帮助调谐共模和/或差模阻抗。

    Printed circuit having ground vias between signal vias
    83.
    发明授权
    Printed circuit having ground vias between signal vias 有权
    印刷电路在信号通孔之间具有接地通孔

    公开(公告)号：US08080738B2

    公开(公告)日：2011-12-20

    申请号：US12572102

    申请日：2009-10-01

    Applicant: Chad W. Morgan

    Inventor： Chad W. Morgan

    IPC: H05K1/16

    CPC classification number: H05K1/0219 ,  H05K1/0245 ,  H05K1/116 ,  H05K2201/09636 ,  H05K2201/10189

    Abstract: A printed circuit includes a substrate having a pair of opposite sides. A signal via extends through at least one of the sides and at least partially through the substrate between the sides. Aggressor vias extend through at least one of the sides and at least partially through the substrate between the sides. The aggressor vias are arranged in a pattern around the signal via. Linear paths are defined between the signal via and the aggressor vias. At least some of the aggressor vias are arranged along the substrate directly adjacent the signal contact. Ground vias extend through at least one of the sides and at least partially through the substrate between the sides. The ground vias are arranged around the signal via. At least one ground via is positioned along each linear path between the signal via and each of the aggressor vias that is directly adjacent the signal via.

    Abstract translation: 印刷电路包括具有一对相对侧的基板。 信号通孔延伸穿过至少一个侧面并且至少部分地穿过侧面之间的衬底。 侵略者通孔延伸穿过至少一个侧面并且至少部分地穿过两侧之间的基底。 侵略者通孔以信号通路周围的图案排列。 在信号通孔和侵略者通孔之间定义线性路径。 至少一些侵略者通孔沿着直接邻近信号触点的衬底排列。 接地通孔延伸穿过侧面中的至少一个并且至少部分地穿过侧面之间的衬底。 接地通孔围绕信号通道排列。 至少一个接地通孔沿着与信号通孔直接相邻的通道和每个侵略通道之间的每个线性路径定位。

    Wiring structure of laminated capacitors
    86.
    发明授权
    Wiring structure of laminated capacitors 有权
    层压电容器的接线结构

    公开(公告)号：US07742276B2

    公开(公告)日：2010-06-22

    申请号：US11950381

    申请日：2007-12-04

    Applicant: Chien-Min Hsu ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lai

    Inventor： Chien-Min Hsu ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lai

    IPC: H01G4/228

    CPC classification number: H05K1/162 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/112 ,  H05K3/429 ,  H05K3/4688 ,  H05K2201/0792 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09636 ,  H05K2201/10734 ,  H01L2224/0401

    Abstract: The present invention relates to a wiring structure for reducing the equivalent series inductance (ESL) of a laminated capacitor. The laminated capacitor comprises a number of conductive layers, a power via extending along a thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer, and a ground via extending along the thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer. The conductive layers include a set of first conductive layers and a set of second conductive layers. The power via is electrically coupled to the first conductive layers and the ground via is electrically coupled to the second conductive layers. The laminated capacitor further comprises a supplemental via between the power via and the ground via. The supplemental via is shorter in length than the power via and the ground via. The supplemental via is electrically coupled to one of the first conductive layers and the second conductive layer.

    Abstract translation: 本发明涉及一种用于降低层叠电容器的等效串联电感（ESL）的布线结构。 层叠电容器包括多个导电层，沿层叠电容器的厚度方向延伸的电力通孔，并且从顶部导电层延伸至底部导电层，沿着层叠电容器的厚度方向延伸的接地通孔 并布置成从顶部导电层延伸到底部导电层。 导电层包括一组第一导电层和一组第二导电层。 电源通孔电耦合到第一导电层，并且接地通孔电耦合到第二导电层。 层叠电容器还包括电源通孔和接地通孔之间的补充通路。 补充通孔的长度要短于电源通孔和接地通孔。 辅助通孔电耦合到第一导电层和第二导电层之一。

    WIRING BOARD HAVING VIA AND METHOD FORMING A VIA IN A WIRING BOARD
    87.
    发明申请
    WIRING BOARD HAVING VIA AND METHOD FORMING A VIA IN A WIRING BOARD 失效
    具有通风方式的接线板和在接线板上形成通风的方法

    公开(公告)号：US20100012366A1

    公开(公告)日：2010-01-21

    申请号：US12501044

    申请日：2009-07-10

    Applicant: Tsutomu Takeda

    Inventor： Tsutomu Takeda

    IPC: H05K1/11 ,  H05K3/02

    CPC classification number: H05K1/115 ,  H05K1/0237 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/09627 ,  H05K2201/09636 ,  H05K2201/09645 ,  H05K2201/09809 ,  H05K2203/0242 ,  H05K2203/175

    Abstract: A wiring board has a plurality of wiring layers, a first land, a second land, a first via and a second via. The first land and the second land are formed on at least one wiring layer of the wiring board and are disposed to partially overlap with each other. The first via and the second via are formed in association with the first land and the second land, respectively. The first via and the second via electrically connect a first wiring layer and a second wiring layer of the plurality of wiring layers to each other. The wiring board has a separator that is formed by a hole that separates the first land and the second land from each other.

    Abstract translation: 布线板具有多个布线层，第一片，第二片，第一片和第二片。 第一焊盘和第二焊盘形成在布线板的至少一个布线层上并且彼此部分地重叠。 第一通孔和第二通孔分别与第一焊盘和第二焊盘相关联地形成。 第一通孔和第二通孔将多个布线层中的第一布线层和第二布线层彼此电连接。 布线板具有由将第一焊盘和第二焊盘彼此分隔开的孔形成的隔板。

    Arrangement of non-signal through vias and wiring board applying the same
    88.
    发明授权
    Arrangement of non-signal through vias and wiring board applying the same 有权
    非信号通孔和布线板的布置

    公开(公告)号：US07615708B2

    公开(公告)日：2009-11-10

    申请号：US11443785

    申请日：2006-05-30

    Applicant: Hsing-Chou Hsu ,  Ying-Ni Lee

    Inventor： Hsing-Chou Hsu ,  Ying-Ni Lee

    IPC: H05K1/11

    CPC classification number: H05K3/4602 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0222 ,  H05K1/0263 ,  H05K1/112 ,  H05K1/115 ,  H05K2201/09536 ,  H05K2201/09636 ,  H05K2201/09781

    Abstract: An arrangement of non-signal through vias suitable for a wiring board is provided. The wiring board has a contact surface, a core layer and pads. The contact pads are disposed on the contact surface, while the arrangement of non-signal through vias includes first non-signal through vias and a second non-signal through via. The first non-signal through vias pass through the core layer and are electrically connected to some of the contact pads. The second non-signal through via which passes through the core layer is disposed between the first non-signal through vias and is not electrically connected to the contact pads. The interval between the second non-signal through via and anyone of the surrounding first non-signal through vias is smaller than or equal to 0.72 times of the minimum interval between any two of the contact pads electrically connected to the corresponding first non-signal through vias.

    Abstract translation: 提供了适用于布线板的非信号通孔的布置。 布线板具有接触表面，芯层和焊盘。 接触焊盘设置在接触表面上，而非信号通孔的布置包括第一非信号通孔和第二非信号通孔。 第一非信号通孔穿过芯层并电连接到一些接触垫。 穿过芯层的第二非信号通孔设置在第一非信号通孔之间，并且不电连接到接触焊盘。 第二非信号通孔与周围的第一非信号通孔之间的间隔小于或等于电连接到相应的第一非信号通孔的任何两个接触焊盘之间的最小间隔的0.72倍 通孔

    Layout configuration of differential signal transmission lines for printed circuit board having offset vias
    89.
    发明授权
    Layout configuration of differential signal transmission lines for printed circuit board having offset vias 失效
    具有偏置通孔的印刷电路板的差分信号传输线的布局配置

    公开(公告)号：US07545233B2

    公开(公告)日：2009-06-09

    申请号：US11446950

    申请日：2006-06-05

    Applicant: Yu-Hsu Lin ,  Shang-Tsang Yeh ,  Chuan-Bing Li

    Inventor： Yu-Hsu Lin ,  Shang-Tsang Yeh ,  Chuan-Bing Li

    IPC: H01P3/04

    CPC classification number: H01P3/081 ,  H01P3/088 ,  H05K1/0245 ,  H05K1/115 ,  H05K2201/09236 ,  H05K2201/09636

    Abstract: A layout configuration of a differential pair for a printed circuit board (PCB) having a signal plane is provided. In a preferred embodiment, the layout configuration comprises: a differential pair on the signal plane; a pair of vias abutting the differential pair, and the pair of vias being mutually dissymmetrical about the differential pair; and a distance between the pair of vias along the differential pair being equal to ½ TV, wherein T is a signal rise time, V is a speed of the signal. Therefore, the layout configuration can meet with the requirements of impedance matching, reduce reflection, and improve signal integrity.

    Abstract translation: 提供了具有信号面的印刷电路板（PCB）的差动对的配置结构。 在优选实施例中，布局配置包括：信号平面上的差分对; 邻接差分对的一对通孔，并且该对通孔围绕差动对相互不对称; 并且沿着差分对的一对通孔之间的距离等于1/2电视，其中T是信号上升时间，V是信号的速度。 因此，布局配置可以满足阻抗匹配的要求，减少反射，提高信号完整性。

Patent Agency Ranking