公开(公告)号：US20050029676A1

公开(公告)日：2005-02-10

申请号：US10936304

申请日：2004-09-07

申请人： Cher Tan ,  Choon Lee ,  Kian Lee ,  Guek Lim ,  Wuu Tay ,  Teck Poh ,  Cheng Pour

发明人： Cher Tan ,  Choon Lee ,  Kian Lee ,  Guek Lim ,  Wuu Tay ,  Teck Poh ,  Cheng Pour

IPC分类号： H01L21/58 ,  H01L23/13 ,  H01L23/16 ,  H01L23/31 ,  H01L23/538 ,  H05K3/30 ,  H05K3/34 ,  H01L23/34

CPC分类号： H01L24/83 ,  B33Y80/00 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/538 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/15787 ,  H01L2924/15788 ,  H05K3/305 ,  H05K3/3452 ,  H05K2201/09036 ,  H05K2201/09909 ,  H05K2201/10689 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A solder mask for use on a carrier substrate includes a device-securing region positionable over at least a portion of a die-support location of the carrier substrate. Dams of the solder mask are positionable laterally adjacent to at least portions of the peripheries of corresponding terminals of the carrier substrate. A carrier substrate includes at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. The solder may be positioned or formed on the carrier substrate. The carrier substrate and solder mask may each include one or more recessed areas that laterally surround at least portions of their die-attach location and device-securing region, respectively, to receive excess adhesive.

摘要翻译： 用于载体衬底的焊接掩模包括可位于载体衬底的管芯支撑位置的至少一部分上的器件固定区域。 焊料掩模的大坝位于横向邻近于载体衬底的相应端子的周边的至少一部分。 载体基板包括至少一个管芯附着位置和从载体衬底的表面突出的一个或多个端子，以防止粘合剂材料污染其连接表面。 焊接掩模可以定位或形成在载体基板上。 载体衬底和焊料掩模可以各自包括一个或多个凹陷区域，其分别横向包围其管芯附接位置和器件固定区域的至少一部分，以容纳多余的粘合剂。

公开(公告)号：US20050287702A1

公开(公告)日：2005-12-29

申请号：US11215628

申请日：2005-08-29

申请人： Cher Victor Tan ,  Choon Lee ,  Kian Lee ,  Guek Lim ,  Wuu Tay ,  Teck Poh ,  Cheng Poh

发明人： Cher Victor Tan ,  Choon Lee ,  Kian Lee ,  Guek Lim ,  Wuu Tay ,  Teck Poh ,  Cheng Poh

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/13 ,  H01L23/498 ,  H05K3/30

CPC分类号： H01L24/97 ,  B33Y80/00 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2224/85385 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H05K3/305 ,  H05K2201/09036 ,  H05K2203/049 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for designing a carrier substrate includes configuring at least one die-attach location and one or more terminals that protrude from a surface of the carrier substrate so as to prevent adhesive material from contaminating connection surfaces thereof. The method may also include configuring the carrier substrate to include one or more recessed areas that laterally surround at least a portion of the die-attach location to receive excess adhesive.

摘要翻译： 一种用于设计载体基板的方法包括：配置至少一个管芯附着位置和从载体衬底的表面突出的一个或多个端子，以防止粘合剂材料污染其连接表面。 该方法还可以包括配置载体衬底以包括一个或多个凹陷区域，该凹陷区域横向围绕裸片附接位置的至少一部分以接收多余的粘合剂。

公开(公告)号：US20060240595A1

公开(公告)日：2006-10-26

申请号：US11474210

申请日：2006-06-22

申请人： Teck Lee ,  Wuu Tay ,  Kian Lee

发明人： Teck Lee ,  Wuu Tay ,  Kian Lee

IPC分类号： H01L21/58

CPC分类号： H01L23/5383 ,  H01L21/563 ,  H01L23/13 ,  H01L23/50 ,  H01L23/5387 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/00

摘要： A method and apparatus for increasing the integrated circuit density in a flip chip semiconductor device assembly including an interposer substrate facilitating use with various semiconductor die conductive bump arrangements. The interposer substrate includes a plurality of recesses formed in at least one of a first surface and a second surface thereof, wherein the recesses are arranged in a plurality of recess patterns. The interposer substrate also provides enhanced accessibility for test probes for electrical testing of the resulting flip chip semiconductor device assembly.

摘要翻译： 一种用于增加包括便于与各种半导体管芯导电凸块布置使用的插入器基板的倒装芯片半导体器件组件中的集成电路密度的方法和装置。 插入器基板包括形成在其第一表面和第二表面中的至少一个中的多个凹部，其中凹部被布置成多个凹陷图案。 插入器基板还为所得到的倒装芯片半导体器件组件的电测试提供了用于测试探针的增强的可访问性。

公开(公告)号：US20050127531A1

公开(公告)日：2005-06-16

申请号：US11041331

申请日：2005-01-24

申请人： Wuu Tay ,  Jeffrey Fook

发明人： Wuu Tay ,  Jeffrey Fook

IPC分类号： G01R1/04 ,  H01L23/31 ,  H01L25/10 ,  H05K1/18 ,  H01L29/40

CPC分类号： H01L23/3114 ,  G01R1/0408 ,  G01R1/0483 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K1/181 ,  H05K2201/10515 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stackable ball grid array (BGA) or fine ball grid array (FBGA) semiconductor package particularly suitable for board-on-chip or chip-on-board applications in which a low profile BGA or FBGA semiconductor package is needed. The stackable ball grid array (BGA) or fine ball grid array (FBGA) provides a semiconductor package that is capable of being burned in and tested in a more efficient and cost effective manner than prior known BGA or FBGA semiconductor packages. A high density, low profile memory module incorporating a plurality of the disclosed BGA or FBGA semiconductor packages in a stacked arrangement is further disclosed.

摘要翻译： 可堆叠球栅阵列（BGA）或细球栅阵列（FBGA）半导体封装，特别适用于需要低剖面BGA或FBGA半导体封装的板上芯片或片上电路板应用。 可堆叠球栅阵列（BGA）或细球栅阵列（FBGA）提供了能够以比现有已知的BGA或FBGA半导体封装更有效和成本有效的方式燃烧和测试的半导体封装。 进一步公开了以堆叠方式并入多个所公开的BGA或FBGA半导体封装的高密度，低轮廓的存储器模块。

公开(公告)号：US20050275116A1

公开(公告)日：2005-12-15

申请号：US11196584

申请日：2005-08-02

申请人： Yong Tan ,  Wuu Tay

发明人： Yong Tan ,  Wuu Tay

IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L21/68 ,  H01L21/76 ,  H01L21/98 ,  H01L23/48 ,  H01L23/544 ,  H01L25/065 ,  H01L29/06 ,  H05B3/68

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68309 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

摘要： Apparatus, systems and methods relating to the reconstruction of semiconductor wafers for wafer-level processing. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice.

摘要翻译： 用于晶片级处理的半导体晶片的重构相关的装置，系统和方法。 将其在其表面中形成的对准空腔的选定的半导体晶片放置成以与基板突出的相似图案中的液体，凝胶或其它可流动的对准液接触，以通过表面张力相互作用来定位骰子。 然后将对准液滴固化以保持定位，并且在骰子和固定装置之间设置底部填充物以加强和维持重建的晶片。 固定板可以与底部填充物组合使用，以增加额外的强度并简化处理。 重构的晶片可以经受晶片级处理，晶片级测试和老化使用重建的晶片特别方便。 由牺牲材料组成的对准液可以从重建的晶片中去除，并且所产生的空隙填充以形成所得骰子上的互连或接触。

公开(公告)号：US20050003575A1

公开(公告)日：2005-01-06

申请号：US10645389

申请日：2003-08-21

申请人： Yong Tan ,  Wuu Tay

发明人： Yong Tan ,  Wuu Tay

IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L21/68 ,  H01L21/76 ,  H01L21/98 ,  H01L23/48 ,  H01L23/544 ,  H01L25/065 ,  H01L29/06 ,  H05B3/68 ,  H01L21/44

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68309 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

摘要： Apparatus, systems and methods relating to the reconstruction of semiconductor wafers for wafer-level processing. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice.

摘要翻译： 用于晶片级处理的半导体晶片的重构相关的装置，系统和方法。 将其在其表面中形成的对准空腔的选定的半导体晶片放置成以与基板突出的相似图案中的液体，凝胶或其它可流动的对准液接触，以通过表面张力相互作用来定位骰子。 然后将对准液滴固化以保持定位，并且在骰子和固定装置之间设置底部填充物以加强和维持重建的晶片。 固定板可以与底部填充物组合使用，以增加额外的强度并简化处理。 重构的晶片可以经受晶片级处理，晶片级测试和老化使用重建的晶片特别方便。 由牺牲材料组成的对准液可以从重建的晶片中去除，并且所产生的空隙填充以形成所得骰子上的互连或接触。

公开(公告)号：US20060240582A1

公开(公告)日：2006-10-26

申请号：US11449472

申请日：2006-06-07

申请人： Yong Tan ,  Wuu Tay

发明人： Yong Tan ,  Wuu Tay

IPC分类号： H01L21/66 ,  H01L21/00 ,  H01L21/30

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68309 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

摘要： Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice.

摘要翻译： 公开了关于用于晶片级处理的半导体晶片的重建的方法。 将其在其表面中形成的对准空腔的选定的半导体晶片放置成以与基板突出的相似图案中的液体，凝胶或其它可流动的对准液接触，以通过表面张力相互作用来定位骰子。 然后将对准液滴固化以保持定位，并且在骰子和固定装置之间设置底部填充物以加强和维持重建的晶片。 固定板可以与底部填充物组合使用，以增加额外的强度并简化处理。 重构的晶片可以经受晶片级处理，晶片级测试和老化使用重建的晶片特别方便。 由牺牲材料组成的对准液可以从重建的晶片中去除，并且所产生的空隙填充以形成所得骰子上的互连或接触。

公开(公告)号：US20050270051A1

公开(公告)日：2005-12-08

申请号：US11197823

申请日：2005-08-05

申请人： Pak Yee ,  Wuu Tay

发明人： Pak Yee ,  Wuu Tay

IPC分类号： G01R31/02 ,  G01R31/26

CPC分类号： G01R31/2875

摘要： A testing apparatus and method for testing integrated circuits is disclosed wherein a device under test is continuously maintained at a desired set point temperature by an included thermal body. The thermal body has an enclosed phase change material which provides latent heat to the device under test such that there is negligible temperature variation realized by integrated circuits being tested.

公开(公告)号：US20050263517A1

公开(公告)日：2005-12-01

申请号：US11196757

申请日：2005-08-02

申请人： Yong Tan ,  Wuu Tay

发明人： Yong Tan ,  Wuu Tay

IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L21/68 ,  H01L21/76 ,  H01L21/98 ,  H01L23/48 ,  H01L23/544 ,  H01L25/065 ,  H01L29/06 ,  H05B3/68

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L23/481 ,  H01L25/0655 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68309 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

摘要： Apparatus, systems and methods relating to the reconstruction of semiconductor wafers for wafer-level processing. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer. Alignment droplets composed of sacrificial material may be removed from the reconstructed wafer and the resulting void filled to form interconnects or contacts on the resulting dice.

摘要翻译： 用于晶片级处理的半导体晶片的重构相关的装置，系统和方法。 将其在其表面中形成的对准空腔的选定的半导体晶片放置成以与基板突出的相似图案中的液体，凝胶或其它可流动的对准液接触，以通过表面张力相互作用来定位骰子。 然后将对准液滴固化以保持定位，并且在骰子和固定装置之间设置底部填充物以加强和维持重建的晶片。 固定板可以与底部填充物组合使用，以增加额外的强度并简化处理。 重构的晶片可以经受晶片级处理，晶片级测试和老化使用重建的晶片特别方便。 由牺牲材料组成的对准液可以从重建的晶片中去除，并且所产生的空隙填充以形成所得骰子上的互连或接触。